mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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63eb8ee533
Define the generic R8A77980 part of the MMC0 (SDHI2) device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
403 lines
12 KiB
Plaintext
403 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a77980 SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/ {
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compatible = "renesas,r8a77980";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0>;
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clocks = <&cpg CPG_CORE 0>;
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power-domains = <&sysc 5>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller {
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compatible = "cache";
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power-domains = <&sysc 21>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77980";
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reg = <0 0xe6060000 0 0x50c>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77980-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77980-rst";
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reg = <0 0xe6160000 0 0x200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77980-sysc";
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reg = <0 0xe6180000 0 0x440>;
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#power-domain-cells = <1>;
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};
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hscif0: serial@e6540000 {
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compatible = "renesas,hscif-r8a77980",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6540000 0 0x60>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 520>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x31>, <&dmac1 0x30>,
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<&dmac2 0x31>, <&dmac2 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 520>;
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status = "disabled";
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};
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hscif1: serial@e6550000 {
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compatible = "renesas,hscif-r8a77980",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6550000 0 0x60>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 519>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x33>, <&dmac1 0x32>,
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<&dmac2 0x33>, <&dmac2 0x32>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 519>;
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status = "disabled";
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};
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hscif2: serial@e6560000 {
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compatible = "renesas,hscif-r8a77980",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6560000 0 0x60>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 518>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x35>, <&dmac1 0x34>,
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<&dmac2 0x35>, <&dmac2 0x34>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 518>;
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status = "disabled";
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};
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hscif3: serial@e66a0000 {
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compatible = "renesas,hscif-r8a77980",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe66a0000 0 0x60>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 517>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x37>, <&dmac1 0x36>,
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<&dmac2 0x37>, <&dmac2 0x36>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 517>;
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status = "disabled";
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77980",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc 32>;
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resets = <&cpg 812>;
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phy-mode = "rgmii";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a77980",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6e60000 0 0x40>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>,
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<&dmac2 0x51>, <&dmac2 0x50>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 207>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a77980",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6e68000 0 0x40>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>,
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<&dmac2 0x53>, <&dmac2 0x52>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 206>;
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status = "disabled";
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};
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scif3: serial@e6c50000 {
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compatible = "renesas,scif-r8a77980",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6c50000 0 0x40>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x57>, <&dmac1 0x56>,
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<&dmac2 0x57>, <&dmac2 0x56>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 204>;
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status = "disabled";
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};
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scif4: serial@e6c40000 {
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compatible = "renesas,scif-r8a77980",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6c40000 0 0x40>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x59>, <&dmac1 0x58>,
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<&dmac2 0x59>, <&dmac2 0x58>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 203>;
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status = "disabled";
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};
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dmac1: dma-controller@e7300000 {
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compatible = "renesas,dmac-r8a77980",
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"renesas,rcar-dmac";
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reg = <0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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dmac2: dma-controller@e7310000 {
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compatible = "renesas,dmac-r8a77980",
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"renesas,rcar-dmac";
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reg = <0 0xe7310000 0 0x10000>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD 217>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 217>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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mmc0: mmc@ee140000 {
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compatible = "renesas,sdhi-r8a77980",
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"renesas,rcar-gen3-sdhi";
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reg = <0 0xee140000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 314>;
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power-domains = <&sysc 32>;
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resets = <&cpg 314>;
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max-frequency = <200000000>;
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status = "disabled";
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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resets = <&cpg 408>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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