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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2af6f5a3fd
Sort subnodes of the soc node. - The primary key is the bus address. - The secondary key is the IP block. - The tertiary key is the node name. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
1077 lines
27 KiB
Plaintext
1077 lines
27 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a77965 SoC
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*
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* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
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*
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* Based on r8a7796.dtsi
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* Copyright (C) 2016 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define CPG_AUDIO_CLK_I 10
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/ {
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compatible = "renesas,r8a77965";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c7 = &i2c_dvfs;
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc 0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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a57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x1>;
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device_type = "cpu";
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power-domains = <&sysc 1>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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L2_CA57: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc 12>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a57_0>,
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<&a57_1>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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wdt0: watchdog@e6020000 {
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reg = <0 0xe6020000 0 0x0c>;
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/* placeholder */
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc 32>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 29>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc 32>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 15>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc 32>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc 32>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 18>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc 32>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc 32>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&sysc 32>;
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resets = <&cpg 906>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a77965",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 4>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 905>;
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power-domains = <&sysc 32>;
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resets = <&cpg 905>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77965";
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reg = <0 0xe6060000 0 0x50c>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77965-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77965-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77965-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc 32>;
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resets = <&cpg 407>;
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};
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i2c0: i2c@e6500000 {
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reg = <0 0xe6500000 0 0x40>;
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/* placeholder */
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};
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i2c1: i2c@e6508000 {
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reg = <0 0xe6508000 0 0x40>;
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/* placeholder */
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};
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i2c2: i2c@e6510000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe6510000 0 0x40>;
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/* placeholder */
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};
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i2c3: i2c@e66d0000 {
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reg = <0 0xe66d0000 0 0x40>;
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/* placeholder */
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};
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i2c4: i2c@e66d8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe66d8000 0 0x40>;
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/* placeholder */
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};
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i2c5: i2c@e66e0000 {
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reg = <0 0xe66e0000 0 0x40>;
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/* placeholder */
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};
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i2c6: i2c@e66e8000 {
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reg = <0 0xe66e8000 0 0x40>;
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/* placeholder */
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};
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i2c_dvfs: i2c@e60b0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a77965",
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"renesas,rcar-gen3-iic",
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"renesas,rmobile-iic";
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reg = <0 0xe60b0000 0 0x425>;
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 926>;
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power-domains = <&sysc 32>;
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resets = <&cpg 926>;
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dmas = <&dmac0 0x11>, <&dmac0 0x10>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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hsusb: usb@e6590000 {
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compatible = "renesas,usbhs-r8a7796",
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"renesas,rcar-gen3-usbhs";
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reg = <0 0xe6590000 0 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 704>;
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dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
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<&usb_dmac1 0>, <&usb_dmac1 1>;
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dma-names = "ch0", "ch1", "ch2", "ch3";
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renesas,buswait = <11>;
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phys = <&usb2_phy0>;
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phy-names = "usb";
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power-domains = <&sysc 32>;
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resets = <&cpg 704>;
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status = "disabled";
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};
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usb_dmac0: dma-controller@e65a0000 {
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compatible = "renesas,r8a77965-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65a0000 0 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 330>;
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power-domains = <&sysc 32>;
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resets = <&cpg 330>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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usb_dmac1: dma-controller@e65b0000 {
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compatible = "renesas,r8a77965-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65b0000 0 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 331>;
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power-domains = <&sysc 32>;
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resets = <&cpg 331>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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usb3_phy0: usb-phy@e65ee000 {
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compatible = "renesas,r8a77965-usb3-phy",
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"renesas,rcar-gen3-usb3-phy";
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reg = <0 0xe65ee000 0 0x90>;
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clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
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<&usb_extal_clk>;
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clock-names = "usb3-if", "usb3s_clk", "usb_extal";
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power-domains = <&sysc 32>;
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resets = <&cpg 328>;
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#phy-cells = <0>;
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status = "disabled";
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a77965",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x10000>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 219>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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dmac1: dma-controller@e7300000 {
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compatible = "renesas,dmac-r8a77965",
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"renesas,rcar-dmac";
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reg = <0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 218>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7310000 {
|
|
compatible = "renesas,dmac-r8a77965",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 217>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 217>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a77965",
|
|
"renesas,etheravb-rcar-gen3";
|
|
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 812>;
|
|
phy-mode = "rgmii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@e6e34000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e34000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@e6e35000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e35000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@e6e36000 {
|
|
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e36000 0 8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
resets = <&cpg 523>;
|
|
power-domains = <&sysc 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 207>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
|
<&dmac2 0x51>, <&dmac2 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 207>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 206>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
|
<&dmac2 0x53>, <&dmac2 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 206>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e88000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e88000 0 64>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 310>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 310>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 204>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 203>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6f30000 {
|
|
compatible = "renesas,scif-r8a77965",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6f30000 0 64>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 202>,
|
|
<&cpg CPG_CORE 20>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
|
|
<&dmac2 0x5b>, <&dmac2 0x5a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 202>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a77965",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6e90000 0 0x0064>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 211>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a77965",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 210>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 210>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a77965",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 209>;
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 209>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a77965",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 208>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin2: video@e6ef2000 {
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin3: video@e6ef3000 {
|
|
reg = <0 0xe6ef3000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin4: video@e6ef4000 {
|
|
reg = <0 0xe6ef4000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin5: video@e6ef5000 {
|
|
reg = <0 0xe6ef5000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin6: video@e6ef6000 {
|
|
reg = <0 0xe6ef6000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
vin7: video@e6ef7000 {
|
|
reg = <0 0xe6ef7000 0 0x1000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
rcar_sound: sound@ec500000 {
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x280>, /* SSI */
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
|
/* placeholder */
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc-0 {
|
|
};
|
|
dvc1: dvc-1 {
|
|
};
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src0: src-0 {
|
|
};
|
|
src1: src-1 {
|
|
};
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi0: ssi-0 {
|
|
};
|
|
ssi1: ssi-1 {
|
|
};
|
|
};
|
|
};
|
|
|
|
xhci0: usb@ee000000 {
|
|
compatible = "renesas,xhci-r8a77965",
|
|
"renesas,rcar-gen3-xhci";
|
|
reg = <0 0xee000000 0 0xc00>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 328>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 328>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_peri0: usb@ee020000 {
|
|
compatible = "renesas,r8a77965-usb3-peri",
|
|
"renesas,rcar-gen3-usb3-peri";
|
|
reg = <0 0xee020000 0 0x400>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 328>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 328>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@ee080000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0xee080000 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
phys = <&usb2_phy0>;
|
|
phy-names = "usb";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@ee0a0000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0xee0a0000 0 0x100>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 702>;
|
|
phys = <&usb2_phy1>;
|
|
phy-names = "usb";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 702>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@ee080100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0xee080100 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
phys = <&usb2_phy0>;
|
|
phy-names = "usb";
|
|
companion = <&ohci0>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@ee0a0100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0xee0a0100 0 0x100>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 702>;
|
|
phys = <&usb2_phy1>;
|
|
phy-names = "usb";
|
|
companion = <&ohci1>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 702>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy0: usb-phy@ee080200 {
|
|
compatible = "renesas,usb2-phy-r8a77965",
|
|
"renesas,rcar-gen3-usb2-phy";
|
|
reg = <0 0xee080200 0 0x700>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 703>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy1: usb-phy@ee0a0200 {
|
|
compatible = "renesas,usb2-phy-r8a77965",
|
|
"renesas,rcar-gen3-usb2-phy";
|
|
reg = <0 0xee0a0200 0 0x700>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 703>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
reg = <0 0xee100000 0 0x2000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
sdhi1: sd@ee120000 {
|
|
reg = <0 0xee120000 0 0x2000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
sdhi2: sd@ee140000 {
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
sdhi3: sd@ee160000 {
|
|
reg = <0 0xee160000 0 0x2000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
gic: interrupt-controller@f1010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1010000 0 0x1000>,
|
|
<0x0 0xf1020000 0 0x20000>,
|
|
<0x0 0xf1040000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x20000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD 408>;
|
|
clock-names = "clk";
|
|
power-domains = <&sysc 32>;
|
|
resets = <&cpg 408>;
|
|
};
|
|
|
|
pciec0: pcie@fe000000 {
|
|
reg = <0 0xfe000000 0 0x80000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
pciec1: pcie@ee800000 {
|
|
reg = <0 0xee800000 0 0x80000>;
|
|
/* placeholder */
|
|
};
|
|
|
|
csi20: csi2@fea80000 {
|
|
reg = <0 0xfea80000 0 0x10000>;
|
|
/* placeholder */
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
csi40: csi2@feaa0000 {
|
|
reg = <0 0xfeaa0000 0 0x10000>;
|
|
/* placeholder */
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
reg = <0 0xfeb00000 0 0x80000>,
|
|
<0 0xfeb90000 0 0x14>;
|
|
/* placeholder */
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb: endpoint {
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_hdmi0: endpoint {
|
|
};
|
|
};
|
|
port@2 {
|
|
reg = <2>;
|
|
du_out_lvds0: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
/* External USB clocks - can be overridden by the board */
|
|
usb3s0_clk: usb3s0 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
usb_extal_clk: usb_extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|