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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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da0159fdb5
On my DRA7 system, when the kernel is built in Thumb-2 mode, the secondary CPU (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This seems to be because the CPU is in ARM mode once the ROM hands over control to the kernel. Switch to Thumb-2 mode if required once the kernel is control of secondary CPU. On OMAP4 on the other hand, it appears to be in Thumb-2 mode on entry so this is not required and SMP boot works as is. Also corrected a spurious '+' and updated copyright information. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
107 lines
3.0 KiB
ArmAsm
107 lines
3.0 KiB
ArmAsm
/*
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* Secondary CPU startup routine source file.
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*
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* Copyright (C) 2009-2014 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include "omap44xx.h"
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define AUX_CORE_BOOT0_PA 0x48281800
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/*
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* OMAP5 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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* register AuxCoreBoot0.
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*/
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ENTRY(omap5_secondary_startup)
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.arm
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THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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ldr r0, [r2]
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mov r0, r0, lsr #5
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne wait
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b secondary_startup
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END(omap5_secondary_startup)
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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* register AuxCoreBoot0.
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*/
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ENTRY(omap4_secondary_startup)
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hold: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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mov r0, r0, lsr #9
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne hold
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/*
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap4_secondary_startup)
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ENTRY(omap4460_secondary_startup)
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hold_2: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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mov r0, r0, lsr #9
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne hold_2
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/*
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* GIC distributor control register has changed between
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* CortexA9 r1pX and r2pX. The Control Register secure
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* banked version is now composed of 2 bits:
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* bit 0 == Secure Enable
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* bit 1 == Non-Secure Enable
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* The Non-Secure banked register has not changed
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* Because the ROM Code is based on the r1pX GIC, the CPU1
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* GIC restoration will cause a problem to CPU0 Non-Secure SW.
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* The workaround must be:
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* 1) Before doing the CPU1 wakeup, CPU0 must disable
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* the GIC distributor
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* 2) CPU1 must re-enable the GIC distributor on
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* it's wakeup path.
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*/
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ldr r1, =OMAP44XX_GIC_DIST_BASE
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ldr r0, [r1]
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orr r0, #1
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str r0, [r1]
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/*
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap4460_secondary_startup)
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