Chris Wilson a4a717010f drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw ... An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably Valleyview) in that for the period following the GPU restart after a reset, there are no GT interrupts received. From Ville's notes, bit 0 in the HWSTAM corresponds to the render interrupt, and if we unmask it we do see immediate resumption of GT interrupt delivery (via the master irq handler) after the reset. v2: Limit the w/a to the render interrupt from rcs Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500 Fixes: c549808946 ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode") References: d420a50c21 ("drm/i915: Clean up the HWSTAM mess") Testcase: igt/gem_eio/reset-stress Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180808105101.913-2-chris@chris-wilson.co.uk		2018-08-08 17:08:07 +01:00
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drm	drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw	2018-08-08 17:08:07 +01:00
host1x	drm for v4.18-rc1	2018-06-06 08:16:33 -07:00
ipu-v3
vga	docs: Fix some broken references	2018-06-15 18:10:01 -03:00
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