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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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76c9dd9dbd
This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
147 lines
4.6 KiB
C
147 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DM365
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk/davinci.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "pll.h"
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#define OCSEL_OCSRC_ENABLE 0
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static const struct davinci_pll_clk_info dm365_pll1_info = {
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.name = "pll1",
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.pllm_mask = GENMASK(9, 0),
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.pllm_min = 1,
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.pllm_max = 1023,
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.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
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PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
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};
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SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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/*
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* This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
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* on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
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* multiplexer. By modeling it as a single parent mux clock, the clock code will
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* still do the right thing in this case.
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*/
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static const char * const dm365_pll_obsclk_parent_names[] = {
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"oscin",
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};
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static u32 dm365_pll_obsclk_table[] = {
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OCSEL_OCSRC_ENABLE,
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};
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static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
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.name = "pll1_obsclk",
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.parent_names = dm365_pll_obsclk_parent_names,
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.num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
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.table = dm365_pll_obsclk_table,
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.ocsrc_mask = BIT(4),
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};
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int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
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clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
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clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
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clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
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davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
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davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
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clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
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davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
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clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
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clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
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davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
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davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
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return 0;
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}
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static const struct davinci_pll_clk_info dm365_pll2_info = {
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.name = "pll2",
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.pllm_mask = GENMASK(9, 0),
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.pllm_min = 1,
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.pllm_max = 1023,
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.flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
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PLL_PLLM_2X,
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};
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
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.name = "pll2_obsclk",
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.parent_names = dm365_pll_obsclk_parent_names,
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.num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
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.table = dm365_pll_obsclk_table,
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.ocsrc_mask = BIT(4),
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};
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int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
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davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
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clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
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clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
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davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
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davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
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davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
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return 0;
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}
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