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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d534b5d4a5
Adding the AHB and APB bus clock for Tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
55 lines
2.1 KiB
C
55 lines
2.1 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA30_CLOCK_H
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#define __MACH_TEGRA30_CLOCK_H
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extern struct clk_ops tegra30_clk_32k_ops;
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extern struct clk_ops tegra30_clk_m_ops;
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extern struct clk_ops tegra_clk_m_div_ops;
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extern struct clk_ops tegra_pll_ref_ops;
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extern struct clk_ops tegra30_pll_ops;
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extern struct clk_ops tegra30_pll_div_ops;
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extern struct clk_ops tegra_plld_ops;
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extern struct clk_ops tegra30_plle_ops;
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extern struct clk_ops tegra_cml_clk_ops;
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extern struct clk_ops tegra_pciex_clk_ops;
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extern struct clk_ops tegra_sync_source_ops;
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extern struct clk_ops tegra30_audio_sync_clk_ops;
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extern struct clk_ops tegra30_clk_double_ops;
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extern struct clk_ops tegra_clk_out_ops;
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extern struct clk_ops tegra30_super_ops;
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extern struct clk_ops tegra30_blink_clk_ops;
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extern struct clk_ops tegra30_twd_ops;
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extern struct clk_ops tegra30_bus_ops;
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extern struct clk_ops tegra30_periph_clk_ops;
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extern struct clk_ops tegra30_dsib_clk_ops;
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extern struct clk_ops tegra_nand_clk_ops;
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extern struct clk_ops tegra_vi_clk_ops;
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extern struct clk_ops tegra_dtv_clk_ops;
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extern struct clk_ops tegra_clk_shared_bus_ops;
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int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
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enum tegra_clk_ex_param p, u32 setting);
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void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
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int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
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enum tegra_clk_ex_param p, u32 setting);
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int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
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enum tegra_clk_ex_param p, u32 setting);
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int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
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enum tegra_clk_ex_param p, u32 setting);
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#endif
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