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29a0e7beab
The L2 RAM is in different power domain from the CPU cluster. So the L2 content can be retained over CPU suspend/resume. To do that, we need to disable L2 after the MMU is disabled, and enable L2 before the MMU is enabled. But the L2 controller is in the same power domain with the CPU cluster. We need to restore it's settings and re-enable it after the power be resumed. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MACH_TEGRA_PM_H_
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#define _MACH_TEGRA_PM_H_
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extern unsigned long l2x0_saved_regs_addr;
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void save_cpu_arch_register(void);
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void restore_cpu_arch_register(void);
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void tegra_clear_cpu_in_lp2(int phy_cpu_id);
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bool tegra_set_cpu_in_lp2(int phy_cpu_id);
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void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
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extern void (*tegra_tear_down_cpu)(void);
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#endif /* _MACH_TEGRA_PM_H_ */
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