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The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Changes by Bartlomiej: - fixed issue with setting lower dividers before the parent clock speed was lowered (the issue resulted in lockup on Exynos4210 SoC based Origen board when "ondemand" cpufreq governor was stress tested) - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change() problem by moving cfg_data search outside of the spin locked area - removed leftover kfree() in exynos_register_cpu_clock() that could result in dereferencing the NULL pointer on error - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers - added missing "last chance" checks to wait_until_divider_stable() and wait_until_mux_stable() (needed in case that IRQ handling took long time to proceed and resulted in function printing incorrect error message about timeout) - moved E4210_CPU_DIV[0,1]() macros just before their only users, this resulted in moving them from patch #2 to patch #3/6 ("clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock") - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV() macros for now - added my Copyrights to drivers/clk/samsung/clk-cpu.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for all PLL's in Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_CPU_H
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#define __SAMSUNG_CLK_CPU_H
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#include "clk.h"
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/**
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* struct exynos_cpuclk_data: config data to setup cpu clocks.
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* @prate: frequency of the primary parent clock (in KHz).
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* @div0: value to be programmed in the div_cpu0 register.
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* @div1: value to be programmed in the div_cpu1 register.
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*
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* This structure holds the divider configuration data for dividers in the CPU
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* clock domain. The parent frequency at which these divider values are valid is
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* specified in @prate. The @prate is the frequency of the primary parent clock.
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* For CPU clock domains that do not have a DIV1 register, the @div1 member
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* value is not used.
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*/
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struct exynos_cpuclk_cfg_data {
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unsigned long prate;
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unsigned long div0;
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unsigned long div1;
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};
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/**
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* struct exynos_cpuclk: information about clock supplied to a CPU core.
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* @hw: handle between CCF and CPU clock.
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* @alt_parent: alternate parent clock to use when switching the speed
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* of the primary parent clock.
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* @ctrl_base: base address of the clock controller.
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* @lock: cpu clock domain register access lock.
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* @cfg: cpu clock rate configuration data.
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* @num_cfgs: number of array elements in @cfg array.
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* @clk_nb: clock notifier registered for changes in clock speed of the
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* primary parent clock.
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* @flags: configuration flags for the CPU clock.
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*
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* This structure holds information required for programming the CPU clock for
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* various clock speeds.
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*/
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struct exynos_cpuclk {
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struct clk_hw hw;
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struct clk *alt_parent;
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void __iomem *ctrl_base;
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spinlock_t *lock;
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const struct exynos_cpuclk_cfg_data *cfg;
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const unsigned long num_cfgs;
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struct notifier_block clk_nb;
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unsigned long flags;
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/* The CPU clock registers has DIV1 configuration register */
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#define CLK_CPU_HAS_DIV1 (1 << 0)
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/* When ALT parent is active, debug clocks need safe divider values */
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#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
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};
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extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name,
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const char *parent, const char *alt_parent,
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unsigned long offset,
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const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags);
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#endif /* __SAMSUNG_CLK_CPU_H */
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