mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 00:35:35 +07:00
863dd269fa
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
138 lines
4.8 KiB
C
138 lines
4.8 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_VCN_H__
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#define __AMDGPU_VCN_H__
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#define AMDGPU_VCN_STACK_SIZE (128*1024)
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#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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#define VCN_DEC_CMD_FENCE 0x00000000
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#define VCN_DEC_CMD_TRAP 0x00000001
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#define VCN_DEC_CMD_WRITE_REG 0x00000004
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#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
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#define VCN_DEC_CMD_PACKET_START 0x0000000a
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#define VCN_DEC_CMD_PACKET_END 0x0000000b
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#define VCN_ENC_CMD_NO_OP 0x00000000
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#define VCN_ENC_CMD_END 0x00000001
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#define VCN_ENC_CMD_IB 0x00000002
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#define VCN_ENC_CMD_FENCE 0x00000003
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#define VCN_ENC_CMD_TRAP 0x00000004
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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enum engine_status_constants {
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
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UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
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UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
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UVD_STATUS__UVD_BUSY = 0x00000004,
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GB_ADDR_CONFIG_DEFAULT = 0x26010011,
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UVD_STATUS__IDLE = 0x2,
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UVD_STATUS__BUSY = 0x5,
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
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UVD_STATUS__RBC_BUSY = 0x1,
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UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
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};
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enum internal_dpg_state {
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VCN_DPG_STATE__UNPAUSE = 0,
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VCN_DPG_STATE__PAUSE,
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};
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struct dpg_pause_state {
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enum internal_dpg_state fw_based;
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enum internal_dpg_state jpeg;
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};
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struct amdgpu_vcn_reg{
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unsigned data0;
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unsigned data1;
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unsigned cmd;
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unsigned nop;
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unsigned scratch9;
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unsigned jpeg_pitch;
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};
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struct amdgpu_vcn {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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unsigned fw_version;
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void *saved_bo;
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struct delayed_work idle_work;
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const struct firmware *fw; /* VCN firmware */
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struct amdgpu_ring ring_dec;
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struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
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struct amdgpu_ring ring_jpeg;
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struct amdgpu_irq_src irq;
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unsigned num_enc_rings;
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enum amd_powergating_state cur_state;
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struct dpg_pause_state pause_state;
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struct amdgpu_vcn_reg internal, external;
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int (*pause_dpg_mode)(struct amdgpu_device *adev,
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struct dpg_pause_state *new_state);
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};
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vcn_suspend(struct amdgpu_device *adev);
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int amdgpu_vcn_resume(struct amdgpu_device *adev);
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void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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#endif
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