mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 03:55:32 +07:00
a58227ef69
A frequent request have been to be able to provide calibration data from a
file as some of the AP devices store the calibration data on an MTD partition.
This patchset adds support for that and also makes it easier to add Device Tree
support later on.
The calibration data is found by using the id string provided by dev_name()
using this format:
cal-<bus>-<id>.bin
With PCI the id string contains bus, slot and func values. For example for a
PCI device in bus 2 slot 0, ath10k will try to retrieve a calibration data from
a file:
/lib/firmware/ath10k/cal-pci-0000:02:00.0.bin
The calibration data sequence is:
1. Check with request_firmware() if there's a calibration file
("cal-<bus>-<id>.bin") on the filesystem for this device. If yes, use that. If
not, goto 2
2. Check if otp.bin is able to successfully load the calibration data
from OTP. If yes, use that. If not, goto 3.
4. Print an error message that no calibration data found and stop driver
initialization for this device.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
382 lines
14 KiB
C
382 lines
14 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HW_H_
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#define _HW_H_
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#include "targaddrs.h"
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#define ATH10K_FW_DIR "ath10k"
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/* QCA988X 1.0 definitions (unsupported) */
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#define QCA988X_HW_1_0_CHIP_ID_REV 0x0
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/* QCA988X 2.0 definitions */
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#define QCA988X_HW_2_0_VERSION 0x4100016c
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#define QCA988X_HW_2_0_CHIP_ID_REV 0x2
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#define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
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#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
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#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
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#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
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#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
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#define ATH10K_FW_API2_FILE "firmware-2.bin"
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#define ATH10K_FW_API3_FILE "firmware-3.bin"
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#define ATH10K_FW_UTF_FILE "utf.bin"
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/* includes also the null byte */
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#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
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#define REG_DUMP_COUNT_QCA988X 60
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#define QCA988X_CAL_DATA_LEN 2116
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struct ath10k_fw_ie {
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__le32 id;
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__le32 len;
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u8 data[0];
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};
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enum ath10k_fw_ie_type {
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ATH10K_FW_IE_FW_VERSION = 0,
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ATH10K_FW_IE_TIMESTAMP = 1,
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ATH10K_FW_IE_FEATURES = 2,
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ATH10K_FW_IE_FW_IMAGE = 3,
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ATH10K_FW_IE_OTP_IMAGE = 4,
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};
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/* Known pecularities:
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* - current FW doesn't support raw rx mode (last tested v599)
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* - current FW dumps upon raw tx mode (last tested v599)
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* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
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* - raw have FCS, nwifi doesn't
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* - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
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* param, llc/snap) are aligned to 4byte boundaries each */
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enum ath10k_hw_txrx_mode {
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ATH10K_HW_TXRX_RAW = 0,
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ATH10K_HW_TXRX_NATIVE_WIFI = 1,
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ATH10K_HW_TXRX_ETHERNET = 2,
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/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
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ATH10K_HW_TXRX_MGMT = 3,
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};
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enum ath10k_mcast2ucast_mode {
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ATH10K_MCAST2UCAST_DISABLED = 0,
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ATH10K_MCAST2UCAST_ENABLED = 1,
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};
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struct ath10k_pktlog_hdr {
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__le16 flags;
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__le16 missed_cnt;
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__le16 log_type;
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__le16 size;
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__le32 timestamp;
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u8 payload[0];
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} __packed;
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/* Target specific defines for MAIN firmware */
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#define TARGET_NUM_VDEVS 8
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#define TARGET_NUM_PEER_AST 2
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#define TARGET_NUM_WDS_ENTRIES 32
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#define TARGET_DMA_BURST_SIZE 0
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#define TARGET_MAC_AGGR_DELIM 0
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#define TARGET_AST_SKID_LIMIT 16
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#define TARGET_NUM_PEERS 16
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#define TARGET_NUM_OFFLOAD_PEERS 0
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#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
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#define TARGET_NUM_PEER_KEYS 2
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#define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS)))
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#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
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#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
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#define TARGET_RX_TIMEOUT_LO_PRI 100
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#define TARGET_RX_TIMEOUT_HI_PRI 40
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/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
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* avoid a very expensive re-alignment in mac80211. */
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#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
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#define TARGET_SCAN_MAX_PENDING_REQS 4
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#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
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#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
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#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
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#define TARGET_GTK_OFFLOAD_MAX_VDEV 3
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#define TARGET_NUM_MCAST_GROUPS 0
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#define TARGET_NUM_MCAST_TABLE_ELEMS 0
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#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
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#define TARGET_TX_DBG_LOG_SIZE 1024
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#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
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#define TARGET_VOW_CONFIG 0
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#define TARGET_NUM_MSDU_DESC (1024 + 400)
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#define TARGET_MAX_FRAG_ENTRIES 0
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/* Target specific defines for 10.X firmware */
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#define TARGET_10X_NUM_VDEVS 16
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#define TARGET_10X_NUM_PEER_AST 2
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#define TARGET_10X_NUM_WDS_ENTRIES 32
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#define TARGET_10X_DMA_BURST_SIZE 0
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#define TARGET_10X_MAC_AGGR_DELIM 0
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#define TARGET_10X_AST_SKID_LIMIT 16
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#define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS))
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#define TARGET_10X_NUM_PEERS_MAX 128
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#define TARGET_10X_NUM_OFFLOAD_PEERS 0
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#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
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#define TARGET_10X_NUM_PEER_KEYS 2
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#define TARGET_10X_NUM_TIDS 256
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#define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
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#define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
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#define TARGET_10X_RX_TIMEOUT_LO_PRI 100
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#define TARGET_10X_RX_TIMEOUT_HI_PRI 40
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#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
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#define TARGET_10X_SCAN_MAX_PENDING_REQS 4
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#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
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#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
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#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
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#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
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#define TARGET_10X_NUM_MCAST_GROUPS 0
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#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
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#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
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#define TARGET_10X_TX_DBG_LOG_SIZE 1024
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#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
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#define TARGET_10X_VOW_CONFIG 0
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#define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
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#define TARGET_10X_MAX_FRAG_ENTRIES 0
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/* Number of Copy Engines supported */
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#define CE_COUNT 8
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/*
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* Total number of PCIe MSI interrupts requested for all interrupt sources.
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* PCIe standard forces this to be a power of 2.
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* Some Host OS's limit MSI requests that can be granted to 8
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* so for now we abide by this limit and avoid requesting more
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* than that.
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*/
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#define MSI_NUM_REQUEST_LOG2 3
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#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
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/*
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* Granted MSIs are assigned as follows:
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* Firmware uses the first
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* Remaining MSIs, if any, are used by Copy Engines
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* This mapping is known to both Target firmware and Host software.
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* It may be changed as long as Host and Target are kept in sync.
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*/
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/* MSI for firmware (errors, etc.) */
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#define MSI_ASSIGN_FW 0
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/* MSIs for Copy Engines */
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#define MSI_ASSIGN_CE_INITIAL 1
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#define MSI_ASSIGN_CE_MAX 7
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/* as of IP3.7.1 */
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#define RTC_STATE_V_ON 3
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#define RTC_STATE_COLD_RESET_MASK 0x00000400
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#define RTC_STATE_V_LSB 0
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#define RTC_STATE_V_MASK 0x00000007
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#define RTC_STATE_ADDRESS 0x0000
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#define PCIE_SOC_WAKE_V_MASK 0x00000001
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#define PCIE_SOC_WAKE_ADDRESS 0x0004
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#define PCIE_SOC_WAKE_RESET 0x00000000
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#define SOC_GLOBAL_RESET_ADDRESS 0x0008
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#define RTC_SOC_BASE_ADDRESS 0x00004000
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#define RTC_WMAC_BASE_ADDRESS 0x00005000
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#define MAC_COEX_BASE_ADDRESS 0x00006000
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#define BT_COEX_BASE_ADDRESS 0x00007000
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#define SOC_PCIE_BASE_ADDRESS 0x00008000
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#define SOC_CORE_BASE_ADDRESS 0x00009000
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#define WLAN_UART_BASE_ADDRESS 0x0000c000
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#define WLAN_SI_BASE_ADDRESS 0x00010000
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#define WLAN_GPIO_BASE_ADDRESS 0x00014000
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#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
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#define WLAN_MAC_BASE_ADDRESS 0x00020000
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#define EFUSE_BASE_ADDRESS 0x00030000
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#define FPGA_REG_BASE_ADDRESS 0x00039000
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#define WLAN_UART2_BASE_ADDRESS 0x00054c00
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#define CE_WRAPPER_BASE_ADDRESS 0x00057000
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#define CE0_BASE_ADDRESS 0x00057400
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#define CE1_BASE_ADDRESS 0x00057800
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#define CE2_BASE_ADDRESS 0x00057c00
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#define CE3_BASE_ADDRESS 0x00058000
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#define CE4_BASE_ADDRESS 0x00058400
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#define CE5_BASE_ADDRESS 0x00058800
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#define CE6_BASE_ADDRESS 0x00058c00
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#define CE7_BASE_ADDRESS 0x00059000
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#define DBI_BASE_ADDRESS 0x00060000
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#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
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#define PCIE_LOCAL_BASE_ADDRESS 0x00080000
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#define SOC_RESET_CONTROL_ADDRESS 0x00000000
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#define SOC_RESET_CONTROL_OFFSET 0x00000000
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#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
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#define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
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#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
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#define SOC_CPU_CLOCK_OFFSET 0x00000020
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#define SOC_CPU_CLOCK_STANDARD_LSB 0
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#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
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#define SOC_CLOCK_CONTROL_OFFSET 0x00000028
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#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
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#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
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#define SOC_LPO_CAL_OFFSET 0x000000e0
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#define SOC_LPO_CAL_ENABLE_LSB 20
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#define SOC_LPO_CAL_ENABLE_MASK 0x00100000
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#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
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#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
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#define SOC_CHIP_ID_ADDRESS 0x000000ec
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#define SOC_CHIP_ID_REV_LSB 8
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#define SOC_CHIP_ID_REV_MASK 0x00000f00
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#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
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#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
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#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
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#define WLAN_GPIO_PIN0_ADDRESS 0x00000028
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#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
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#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
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#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
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#define WLAN_GPIO_PIN10_ADDRESS 0x00000050
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#define WLAN_GPIO_PIN11_ADDRESS 0x00000054
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#define WLAN_GPIO_PIN12_ADDRESS 0x00000058
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#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
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#define CLOCK_GPIO_OFFSET 0xffffffff
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#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
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#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
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#define SI_CONFIG_OFFSET 0x00000000
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#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
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#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
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#define SI_CONFIG_I2C_LSB 16
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#define SI_CONFIG_I2C_MASK 0x00010000
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#define SI_CONFIG_POS_SAMPLE_LSB 7
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#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
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#define SI_CONFIG_INACTIVE_DATA_LSB 5
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#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
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#define SI_CONFIG_INACTIVE_CLK_LSB 4
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#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
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#define SI_CONFIG_DIVIDER_LSB 0
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#define SI_CONFIG_DIVIDER_MASK 0x0000000f
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#define SI_CS_OFFSET 0x00000004
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#define SI_CS_DONE_ERR_MASK 0x00000400
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#define SI_CS_DONE_INT_MASK 0x00000200
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#define SI_CS_START_LSB 8
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#define SI_CS_START_MASK 0x00000100
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#define SI_CS_RX_CNT_LSB 4
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#define SI_CS_RX_CNT_MASK 0x000000f0
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#define SI_CS_TX_CNT_LSB 0
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#define SI_CS_TX_CNT_MASK 0x0000000f
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#define SI_TX_DATA0_OFFSET 0x00000008
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#define SI_TX_DATA1_OFFSET 0x0000000c
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#define SI_RX_DATA0_OFFSET 0x00000010
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#define SI_RX_DATA1_OFFSET 0x00000014
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#define CORE_CTRL_CPU_INTR_MASK 0x00002000
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#define CORE_CTRL_ADDRESS 0x0000
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#define PCIE_INTR_ENABLE_ADDRESS 0x0008
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#define PCIE_INTR_CAUSE_ADDRESS 0x000c
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#define PCIE_INTR_CLR_ADDRESS 0x0014
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#define SCRATCH_3_ADDRESS 0x0030
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#define CPU_INTR_ADDRESS 0x0010
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/* Firmware indications to the Host via SCRATCH_3 register. */
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#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
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#define FW_IND_EVENT_PENDING 1
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#define FW_IND_INITIALIZED 2
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/* HOST_REG interrupt from firmware */
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#define PCIE_INTR_FIRMWARE_MASK 0x00000400
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#define PCIE_INTR_CE_MASK_ALL 0x0007f800
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#define DRAM_BASE_ADDRESS 0x00400000
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#define MISSING 0
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#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
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#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
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#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
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#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
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#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
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#define RESET_CONTROL_MBOX_RST_MASK MISSING
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#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
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#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
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#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
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#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
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#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
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#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
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#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
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#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
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#define LOCAL_SCRATCH_OFFSET 0x18
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#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
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#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
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#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
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#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
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#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
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#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
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#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
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#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
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#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
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#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
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#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
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#define MBOX_BASE_ADDRESS MISSING
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#define INT_STATUS_ENABLE_ERROR_LSB MISSING
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#define INT_STATUS_ENABLE_ERROR_MASK MISSING
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#define INT_STATUS_ENABLE_CPU_LSB MISSING
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#define INT_STATUS_ENABLE_CPU_MASK MISSING
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#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
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#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
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#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
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#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
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#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
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#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
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#define INT_STATUS_ENABLE_ADDRESS MISSING
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#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
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#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
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#define HOST_INT_STATUS_ADDRESS MISSING
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#define CPU_INT_STATUS_ADDRESS MISSING
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#define ERROR_INT_STATUS_ADDRESS MISSING
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#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
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#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
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#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
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#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
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#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
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#define COUNT_DEC_ADDRESS MISSING
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#define HOST_INT_STATUS_CPU_MASK MISSING
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#define HOST_INT_STATUS_CPU_LSB MISSING
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#define HOST_INT_STATUS_ERROR_MASK MISSING
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#define HOST_INT_STATUS_ERROR_LSB MISSING
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#define HOST_INT_STATUS_COUNTER_MASK MISSING
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#define HOST_INT_STATUS_COUNTER_LSB MISSING
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#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
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#define WINDOW_DATA_ADDRESS MISSING
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#define WINDOW_READ_ADDR_ADDRESS MISSING
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#define WINDOW_WRITE_ADDR_ADDRESS MISSING
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#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
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#endif /* _HW_H_ */
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