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linux_dsm_epyc7002/arch/arm/boot/dts/imx51-ts4800.dts
Marco Franchi f7059428ec ARM: dts: imx51: Fix inconsistent display port names 
Contrary to later i.MX SoCs, the parallel display interface pad groups on
i.MX51 are called DISP1 and DISP2 in the Reference Manual, not DISP0 and
DISP1.

Fix this inconsistence by changing the DISP names in the i.mx51 dts.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-10-13 15:58:42 +08:00

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/*
* Copyright 2015 Savoir-faire Linux
*
* This device tree is based on imx51-babbage.dts
*
* Licensed under the X11 license or the GPL v2 (or later)
*/
/dts-v1/;
#include "imx51.dtsi"
/ {
model = "Technologic Systems TS-4800";
compatible = "technologic,imx51-ts4800", "fsl,imx51";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x90000000 0x10000000>;
};
clocks {
ckih1 {
clock-frequency = <22579200>;
};
ckih2 {
clock-frequency = <24576000>;
};
};
backlight_reg: regulator-backlight {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_lcd>;
regulator-name = "enable_lcd_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 78770>;
brightness-levels = <0 150 200 255>;
default-brightness-level = <1>;
power-supply = <&backlight_reg>;
};
display1: disp1 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
display-timings {
800x480p60 {
native-mode;
clock-frequency = <30066000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <50>;
hback-porch = <70>;
hsync-len = <50>;
vback-porch = <0>;
vfront-porch = <0>;
vsync-len = <50>;
};
};
port@0 {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp1>;
};
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
rtc: m41t00@68 {
compatible = "st,m41t00";
reg = <0x68>;
};
};
&ipu_di0_disp1 {
remote-endpoint = <&display0_in>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_backlight>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
fpga@0 {
compatible = "simple-bus";
fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
0x00000000 0x1c092480 0x00000000>;
reg = <0 0x0000000 0x1d000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x1d000>;
syscon: syscon@b0010000 {
compatible = "syscon", "simple-mfd";
reg = <0x10000 0x3d>;
reg-io-width = <2>;
wdt@e {
compatible = "technologic,ts4800-wdt";
syscon = <&syscon 0xe>;
};
};
touchscreen {
compatible = "technologic,ts4800-ts";
reg = <0x12000 0x1000>;
syscon = <&syscon 0x10 6>;
};
fpga_irqc: fpga-irqc@15000 {
compatible = "technologic,ts4800-irqc";
reg = <0x15000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_interrupt_fpga>;
interrupt-parent = <&gpio2>;
interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
can@1a000 {
compatible = "technologic,sja1000";
reg = <0x1a000 0x100>;
interrupt-parent = <&fpga_irqc>;
interrupts = <1>;
reg-io-width = <2>;
nxp,tx-output-config = <0x06>;
nxp,external-clock-frequency = <24000000>;
};
};
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
>;
};
pinctrl_enable_lcd: enablelcdgrp {
fsl,pins = <
MX51_PAD_CSI2_D12__GPIO4_9 0x1c5
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
MX51_PAD_GPIO1_0__GPIO1_0 0x100
MX51_PAD_GPIO1_1__GPIO1_1 0x100
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_interrupt_fpga: fpgaicgrp {
fsl,pins = <
MX51_PAD_EIM_D27__GPIO2_9 0xe5
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
MX51_PAD_DI_GP4__DI2_PIN15 0x5
>;
};
pinctrl_pwm_backlight: backlightgrp {
fsl,pins = <
MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX51_PAD_EIM_DTACK__EIM_DTACK 0x85
MX51_PAD_EIM_CS0__EIM_CS0 0x0
MX51_PAD_EIM_CS1__EIM_CS1 0x0
MX51_PAD_EIM_EB0__EIM_EB0 0x85
MX51_PAD_EIM_EB1__EIM_EB1 0x85
MX51_PAD_EIM_OE__EIM_OE 0x85
MX51_PAD_EIM_LBA__EIM_LBA 0x85
>;
};
};
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