AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
a3eec13b8f
linux_dsm_epyc7002/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
Linus Torvalds 6ad63dec9c ARM: SoC device tree updates for 5.1 
This is a smaller update than the past few times, but with just over
 500 non-merge changesets still dwarfes the rest of the SoC tree.
 
 Three new SoC platforms get added, each one a follow-up to an existing
 product, and added here in combination with a reference platform:
 
  - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor
    https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
 
  - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for
    Rich Graphics Applications".
    https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
 
  - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
 
 These are actual commercial products we now support with an in-kernel
 device tree source file:
 
  - Bosch Guardian is a product made by Bosch Power
    Tools GmbH, based on the Texas Instruments AM335x chip
 
  - Winterland IceBoard is a Texas Instruments AM3874 based
    machine used in telescopes at the south pole and elsewhere, see commit
    d031773169 for some pointers:
 
  - Inspur on5263m5 is an x86 server platform with an Aspeed
    ast2500 baseboard management controller. This is for running on
    the BMC.
 
  - Zodiac Digital Tapping Unit, apparently a kind of ethernet
    switch used in airplanes.
 
  - Phicomm K3 is a WiFi router based on Broadcom bcm47094
 
  - Methode Electronics uDPU FTTdp distribution point unit
 
  - X96 Max, a generic TV box based on Amlogic G12a (S905X2)
 
  - NVIDIA Shield TV (Darcy) based on Tegra210
 
 And then there are several new SBC, evaluation, development or modular
 systems that we add:
 
  - Three new Rockchips rk3399 based boards:
     - FriendlyElec NanoPC-T4 and NanoPi M4
     - Radxa ROCK Pi 4
 
  - Five new i.MX6 family SoM modules and boards for industrial
    products:
     - Logic PD i.MX6QD SoM and evaluation baseboad
     - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
     - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module
 
  - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
    microcontroller
 
  - Chameleon96, an Intel/Altera Cyclone5 based FPGA development
    system in 96boards form factor
 
  - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely
    virtual platform for corresponding to the latest "fast model"
 
  - Another Raspberry Pi variant: Model 3 A+, supported both
    in 32-bit and 64-bit mode.
 
  - Oxalis Evalkit V100 based on NXP Layerscape LS1012a,
    in 96Boards enterprise form factor
 
  - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108
 
 For already supported boards and SoCs, we often add support for new
 devices after merging the drivers. This time, the largest changes include
 updates for
 
  - STMicroelectronics stm32mp1, which was now formally
    launched last week
 
  - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip
 
  - Action Semi S700
 
  - TI AM654x, their recently merged 64-bit SoC from the OMAP family
 
  - Various Amlogic Meson SoCs
 
  - Mediatek MT2712
 
  - NVIDIA Tegra186 and Tegra210
 
  - The ancient NXP lpc32xx family
 
  - Samsung s5pv210, used in some older mobile phones
 
 Many other chips see smaller updates and bugfixes beyond that.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJcf9c1AAoJEGCrR//JCVInvl8QAIgmK09QZr3VAD5WnKSoWwiX
 GP1+qgmr/cbIF9X+Kt/0Y2E+oIi9uxu7v5iwpYf0inzV4QOKwy9LvpeInd7s07bf
 hSPMN0wZ9bV5Ylk0YtlvGvOQTqys9oweeSEkHfjQ8Jm7aFkaRXQ1dt23d8KLILoB
 8GKk9A4ncn1AB1vu6xBqeqBiaQiqhMjb9paWkmjYrjhP22hHlVyGlMd8cwfG+A5a
 5Ft4lWkzvgrXPMwZgrCGU233OV5UHrn2A8ohiIUN5J6aSWxu8eMEryU+MF0poidl
 malJ+AHl2mK83YN3wYemxy/lEJzAW4PrjCVgY2bRDqwlOnI3+d+z7rVSfuMCzSKs
 TDTbv9VqPJhsZFr/GIkvB3iwnYfvP/mXrzM7gbw7rQqthEKOy+3HtZwmHAKF4QNK
 TT4wyngC/CwiyULEwtPCjbxZ/7yal6sygllioCo+M2OHeattIQEnqi/Yvc0vx/th
 th9Pepf26jUp/ZJNlxk0XDyBMPhUf6sHUvh7a+y6l6ZxZ6avbFdGPeJrQe5HF2Sp
 KM7BH3w/CpoNRSKs37mR7JpNdYNDSonItgaIm5xVJZk+Wr/BWgtcr6BbGD/vlT7N
 kIDDinyhczhvhpTmWs6QZdZNQmf6bASzTVeFv2+ES+kXt/AKhv0O5N4Pw/oU+VBv
 pD5+7YjjA0fMKcYae3gs
 =1goV
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC device tree updates from Arnd Bergmann:
 "This is a smaller update than the past few times, but with just over
  500 non-merge changesets still dwarfes the rest of the SoC tree.

  Three new SoC platforms get added, each one a follow-up to an existing
  product, and added here in combination with a reference platform:

   - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging
     processor:

       https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html

   - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics
     Applications":

       https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html

   - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC:

       https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X

  These are actual commercial products we now support with an in-kernel
  device tree source file:

   - Bosch Guardian is a product made by Bosch Power Tools GmbH, based
     on the Texas Instruments AM335x chip

   - Winterland IceBoard is a Texas Instruments AM3874 based machine
     used in telescopes at the south pole and elsewhere, see commit
     d031773169 for some pointers:

   - Inspur on5263m5 is an x86 server platform with an Aspeed ast2500
     baseboard management controller. This is for running on the BMC.

   - Zodiac Digital Tapping Unit, apparently a kind of ethernet switch
     used in airplanes.

   - Phicomm K3 is a WiFi router based on Broadcom bcm47094

   - Methode Electronics uDPU FTTdp distribution point unit

   - X96 Max, a generic TV box based on Amlogic G12a (S905X2)

   - NVIDIA Shield TV (Darcy) based on Tegra210

  And then there are several new SBC, evaluation, development or modular
  systems that we add:

   - Three new Rockchips rk3399 based boards:
       - FriendlyElec NanoPC-T4 and NanoPi M4
       - Radxa ROCK Pi 4

   - Five new i.MX6 family SoM modules and boards for industrial
     products:
       - Logic PD i.MX6QD SoM and evaluation baseboad
       - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
       - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module

   - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
     microcontroller

   - Chameleon96, an Intel/Altera Cyclone5 based FPGA development system
     in 96boards form factor

   - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual
     platform for corresponding to the latest "fast model"

   - Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit
     and 64-bit mode.

   - Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards
     enterprise form factor

   - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108

  For already supported boards and SoCs, we often add support for new
  devices after merging the drivers. This time, the largest changes
  include updates for

   - STMicroelectronics stm32mp1, which was now formally launched last
     week

   - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip

   - Action Semi S700

   - TI AM654x, their recently merged 64-bit SoC from the OMAP family

   - Various Amlogic Meson SoCs

   - Mediatek MT2712

   - NVIDIA Tegra186 and Tegra210

   - The ancient NXP lpc32xx family

   - Samsung s5pv210, used in some older mobile phones

  Many other chips see smaller updates and bugfixes beyond that"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits)
  ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4
  dt-bindings: net: ti: deprecate cpsw-phy-sel bindings
  ARM: dts: am335x: switch to use phy-gmii-sel
  ARM: dts: am4372: switch to use phy-gmii-sel
  ARM: dts: dm814x: switch to use phy-gmii-sel
  ARM: dts: dra7: switch to use phy-gmii-sel
  arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference
  ARM: dts: exynos: Add support for secondary DAI to Odroid XU4
  ARM: dts: exynos: Add support for secondary DAI to Odroid XU3
  ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite
  ARM: dts: exynos: Add stdout path property to Arndale board
  ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU
  ARM: dts: exynos: Enable ADC on Odroid HC1
  arm64: dts: sprd: Remove wildcard compatible string
  arm64: dts: sprd: Add SC27XX fuel gauge device
  arm64: dts: sprd: Add SC2731 charger device
  arm64: dts: sprd: Add ADC calibration support
  arm64: dts: sprd: Remove PMIC INTC irq trigger type
  arm64: dts: rockchip: Enable tsadc device on rock960
  ARM: dts: rockchip: add chosen node on veyron devices
  ...
2019-03-06 09:36:37 -08:00

351 lines
8.3 KiB
Plaintext
Raw Blame History

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017 NXP
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "NXP i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
n25q256a: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdog1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
Reference in New Issue View Git Blame Copy Permalink