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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 00:16:42 +07:00
b7f8101d6e
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* based on drivers/clk/tegra/clk.h
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef __SOCFPGA_CLK_H
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#define __SOCFPGA_CLK_H
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#include <linux/clk-provider.h>
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/* Clock Manager offsets */
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#define CLKMGR_CTRL 0x0
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#define CLKMGR_BYPASS 0x4
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#define CLKMGR_DBCTRL 0x10
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#define CLKMGR_L4SRC 0x70
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#define CLKMGR_PERPLL_SRC 0xAC
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#define SOCFPGA_MAX_PARENTS 5
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#define streq(a, b) (strcmp((a), (b)) == 0)
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
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#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
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((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
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extern void __iomem *clk_mgr_base_addr;
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extern void __iomem *clk_mgr_a10_base_addr;
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void __init socfpga_pll_init(struct device_node *node);
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void __init socfpga_periph_init(struct device_node *node);
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void __init socfpga_gate_init(struct device_node *node);
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void socfpga_a10_pll_init(struct device_node *node);
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void socfpga_a10_periph_init(struct device_node *node);
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void socfpga_a10_gate_init(struct device_node *node);
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struct socfpga_pll {
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struct clk_gate hw;
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};
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struct socfpga_gate_clk {
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struct clk_gate hw;
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char *parent_name;
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u32 fixed_div;
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void __iomem *div_reg;
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struct regmap *sys_mgr_base_addr;
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u32 width; /* only valid if div_reg != 0 */
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u32 shift; /* only valid if div_reg != 0 */
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u32 clk_phase[2];
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};
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struct socfpga_periph_clk {
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struct clk_gate hw;
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char *parent_name;
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u32 fixed_div;
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void __iomem *div_reg;
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u32 width; /* only valid if div_reg != 0 */
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u32 shift; /* only valid if div_reg != 0 */
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};
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#endif /* SOCFPGA_CLK_H */
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