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c0d6fe2f01
As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here.) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWQT2WAAoJEIwa5zzehBx37tgQAIBe5eDJFXFihTlyOQ2plL3q vVH4OCzXIHELfM1J8CGZNah1wCQqNOts8RAmDCzxr+zSYuLOwJOEDZ6NKmErMxl0 NTj3+BsqKO3NRym970ofPqU9JRLQmpZ8K7dzk8Nwj2+r1WZHFu/j6Jv44n/Ns0lw 7+wxnG322lTm7SnvALCMD5lD4Y7VpThooWy5SdFtRoAetn+cLbVCJIeeQvO6Vxkp NooeJR0t2e8cpbAND5Jwu6eeWRcIbrvgjYDe0omhrIY05i9yNvIsC2HuQFGjF43z p2CnQvcKnhOXTZw3yse1Fx5igA7jqwVjjC/lVeDyxhusAtLpmuB6qbSaj7DpqkSQ nJxX1d49WKm68K+aknmee1kYRrvc4DE/kORI4IxXnsVNMu16ifTVLnxKgUhwzukb eZdTP6rsqgNozaYvh0k1vfSFd+CNSkBg+E9nrI3tU95yo3LOIhobVBCvBcWlmUvQ JdavRztqosChjIx3a9i1eCNKJtCg9p4m+gWjUqVVWsxBHe/3HojzjZnsBSynIQMA uGIVm0TKhNl1Svxl3oJo9257UCUK7+5PqJHK9IHrcWDULYx05JGSjuZcyvNS6Fo+ u1DMf0ud4gXJYhecFBa7b3zRjk5YxptgCCTjeEEOTUJbbhZqDjGFZlNuFi6dmqD3 ILJ2QMe/DGiPIlUmCfsx =qY1q -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
1467 lines
36 KiB
Plaintext
1467 lines
36 KiB
Plaintext
/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3288";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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mshc0 = &emmc;
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mshc1 = &sdmmc;
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mshc2 = &sdio0;
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mshc3 = &sdio1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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};
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arm-pmu {
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compatible = "arm,cortex-a12-pmu";
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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rockchip,pmu = <&pmu>;
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cpu0: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x500>;
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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1608000 1350000
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1512000 1300000
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1416000 1200000
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1200000 1100000
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1008000 1050000
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816000 1000000
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696000 950000
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600000 900000
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408000 900000
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312000 900000
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216000 900000
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126000 900000
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>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x501>;
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resets = <&cru SRST_CORE1>;
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};
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cpu2: cpu@502 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x502>;
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resets = <&cru SRST_CORE2>;
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};
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cpu3: cpu@503 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x503>;
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resets = <&cru SRST_CORE3>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff250000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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dmac_bus_ns: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff600000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dmac_bus_s: dma-controller@ffb20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffb20000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* The rk3288 cannot use the memory area above 0xfe000000
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* for dma operations for some reason. While there is
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* probably a better solution available somewhere, we
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* haven't found it yet and while devices with 2GB of ram
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* are not affected, this issue prevents 4GB from booting.
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* So to make these devices at least bootable, block
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* this area for the time being until the real solution
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* is found.
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*/
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dma-unusable@fe000000 {
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reg = <0xfe000000 0x1000000>;
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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timer: timer@ff810000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0xff810000 0x20>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vopl_out>, <&vopb_out>;
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};
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sdmmc: dwmmc@ff0c0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0c0000 0x4000>;
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status = "disabled";
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};
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sdio0: dwmmc@ff0d0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0d0000 0x4000>;
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status = "disabled";
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};
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sdio1: dwmmc@ff0e0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
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<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0e0000 0x4000>;
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status = "disabled";
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};
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emmc: dwmmc@ff0f0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xff0f0000 0x4000>;
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status = "disabled";
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};
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saradc: saradc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0xff100000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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spi0: spi@ff110000 {
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compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac_peri 11>, <&dmac_peri 12>;
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dma-names = "tx", "rx";
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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reg = <0xff110000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@ff120000 {
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compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac_peri 13>, <&dmac_peri 14>;
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dma-names = "tx", "rx";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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reg = <0xff120000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@ff130000 {
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compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac_peri 15>, <&dmac_peri 16>;
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dma-names = "tx", "rx";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
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reg = <0xff130000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@ff140000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff140000 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff150000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff150000 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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i2c4: i2c@ff160000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff160000 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C4>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff170000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C5>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff180000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@ff190000 {
|
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
|
reg = <0xff190000 0x100>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ff690000 {
|
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
|
reg = <0xff690000 0x100>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@ff1b0000 {
|
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
|
reg = <0xff1b0000 0x100>;
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@ff1c0000 {
|
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
|
reg = <0xff1c0000 0x100>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal-zones {
|
|
#include "rk3288-thermal.dtsi"
|
|
};
|
|
|
|
tsadc: tsadc@ff280000 {
|
|
compatible = "rockchip,rk3288-tsadc";
|
|
reg = <0xff280000 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&otp_out>;
|
|
#thermal-sensor-cells = <1>;
|
|
rockchip,hw-tshut-temp = <95000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac: ethernet@ff290000 {
|
|
compatible = "rockchip,rk3288-gmac";
|
|
reg = <0xff290000 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru SCLK_MAC>,
|
|
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
|
|
<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
|
|
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
|
|
clock-names = "stmmaceth",
|
|
"mac_clk_rx", "mac_clk_tx",
|
|
"clk_mac_ref", "clk_mac_refout",
|
|
"aclk_mac", "pclk_mac";
|
|
resets = <&cru SRST_MAC>;
|
|
reset-names = "stmmaceth";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ehci: usb@ff500000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0xff500000 0x100>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_USBHOST0>;
|
|
clock-names = "usbhost";
|
|
phys = <&usbphy1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* NOTE: ohci@ff520000 doesn't actually work on hardware */
|
|
|
|
usb_host1: usb@ff540000 {
|
|
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
|
"snps,dwc2";
|
|
reg = <0xff540000 0x40000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_USBHOST1>;
|
|
clock-names = "otg";
|
|
dr_mode = "host";
|
|
phys = <&usbphy2>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_otg: usb@ff580000 {
|
|
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
|
"snps,dwc2";
|
|
reg = <0xff580000 0x40000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_OTG0>;
|
|
clock-names = "otg";
|
|
dr_mode = "otg";
|
|
g-np-tx-fifo-size = <16>;
|
|
g-rx-fifo-size = <275>;
|
|
g-tx-fifo-size = <256 128 128 64 64 32>;
|
|
g-use-dma;
|
|
phys = <&usbphy0>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_hsic: usb@ff5c0000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0xff5c0000 0x100>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HSIC>;
|
|
clock-names = "usbhost";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ff650000 {
|
|
compatible = "rockchip,rk3288-i2c";
|
|
reg = <0xff650000 0x1000>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@ff660000 {
|
|
compatible = "rockchip,rk3288-i2c";
|
|
reg = <0xff660000 0x1000>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff680000 {
|
|
compatible = "rockchip,rk3288-pwm";
|
|
reg = <0xff680000 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&cru PCLK_PWM>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff680010 {
|
|
compatible = "rockchip,rk3288-pwm";
|
|
reg = <0xff680010 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&cru PCLK_PWM>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff680020 {
|
|
compatible = "rockchip,rk3288-pwm";
|
|
reg = <0xff680020 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_pin>;
|
|
clocks = <&cru PCLK_PWM>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff680030 {
|
|
compatible = "rockchip,rk3288-pwm";
|
|
reg = <0xff680030 0x10>;
|
|
#pwm-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_pin>;
|
|
clocks = <&cru PCLK_PWM>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_intmem@ff700000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xff700000 0x18000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xff700000 0x18000>;
|
|
smp-sram@0 {
|
|
compatible = "rockchip,rk3066-smp-sram";
|
|
reg = <0x00 0x10>;
|
|
};
|
|
};
|
|
|
|
sram@ff720000 {
|
|
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
|
|
reg = <0xff720000 0x1000>;
|
|
};
|
|
|
|
pmu: power-management@ff730000 {
|
|
compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
|
|
reg = <0xff730000 0x100>;
|
|
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3288-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/*
|
|
* Note: Although SCLK_* are the working clocks
|
|
* of device without including on the NOC, needed for
|
|
* synchronous reset.
|
|
*
|
|
* The clocks on the which NOC:
|
|
* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
|
|
* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
|
|
* ACLK_RGA is on ACLK_RGA_NIU.
|
|
* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
|
|
*
|
|
* Which clock are device clocks:
|
|
* clocks devices
|
|
* *_IEP IEP:Image Enhancement Processor
|
|
* *_ISP ISP:Image Signal Processing
|
|
* *_VIP VIP:Video Input Processor
|
|
* *_VOP* VOP:Visual Output Processor
|
|
* *_RGA RGA
|
|
* *_EDP* EDP
|
|
* *_LVDS_* LVDS
|
|
* *_HDMI HDMI
|
|
* *_MIPI_* MIPI
|
|
*/
|
|
pd_vio {
|
|
reg = <RK3288_PD_VIO>;
|
|
clocks = <&cru ACLK_IEP>,
|
|
<&cru ACLK_ISP>,
|
|
<&cru ACLK_RGA>,
|
|
<&cru ACLK_VIP>,
|
|
<&cru ACLK_VOP0>,
|
|
<&cru ACLK_VOP1>,
|
|
<&cru DCLK_VOP0>,
|
|
<&cru DCLK_VOP1>,
|
|
<&cru HCLK_IEP>,
|
|
<&cru HCLK_ISP>,
|
|
<&cru HCLK_RGA>,
|
|
<&cru HCLK_VIP>,
|
|
<&cru HCLK_VOP0>,
|
|
<&cru HCLK_VOP1>,
|
|
<&cru PCLK_EDP_CTRL>,
|
|
<&cru PCLK_HDMI_CTRL>,
|
|
<&cru PCLK_LVDS_PHY>,
|
|
<&cru PCLK_MIPI_CSI>,
|
|
<&cru PCLK_MIPI_DSI0>,
|
|
<&cru PCLK_MIPI_DSI1>,
|
|
<&cru SCLK_EDP_24M>,
|
|
<&cru SCLK_EDP>,
|
|
<&cru SCLK_ISP_JPE>,
|
|
<&cru SCLK_ISP>,
|
|
<&cru SCLK_RGA>;
|
|
};
|
|
|
|
/*
|
|
* Note: The following 3 are HEVC(H.265) clocks,
|
|
* and on the ACLK_HEVC_NIU (NOC).
|
|
*/
|
|
pd_hevc {
|
|
reg = <RK3288_PD_HEVC>;
|
|
clocks = <&cru ACLK_HEVC>,
|
|
<&cru SCLK_HEVC_CABAC>,
|
|
<&cru SCLK_HEVC_CORE>;
|
|
};
|
|
|
|
/*
|
|
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
|
|
* (video endecoder & decoder) clocks that on the
|
|
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
|
|
*/
|
|
pd_video {
|
|
reg = <RK3288_PD_VIDEO>;
|
|
clocks = <&cru ACLK_VCODEC>,
|
|
<&cru HCLK_VCODEC>;
|
|
};
|
|
|
|
/*
|
|
* Note: ACLK_GPU is the GPU clock,
|
|
* and on the ACLK_GPU_NIU (NOC).
|
|
*/
|
|
pd_gpu {
|
|
reg = <RK3288_PD_GPU>;
|
|
clocks = <&cru ACLK_GPU>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sgrf: syscon@ff740000 {
|
|
compatible = "rockchip,rk3288-sgrf", "syscon";
|
|
reg = <0xff740000 0x1000>;
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3288-cru";
|
|
reg = <0xff760000 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
|
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
|
|
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
|
|
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
|
|
<&cru PCLK_PERI>;
|
|
assigned-clock-rates = <594000000>, <400000000>,
|
|
<500000000>, <300000000>,
|
|
<150000000>, <75000000>,
|
|
<300000000>, <150000000>,
|
|
<75000000>;
|
|
};
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3288-grf", "syscon";
|
|
reg = <0xff770000 0x1000>;
|
|
};
|
|
|
|
wdt: watchdog@ff800000 {
|
|
compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
|
|
reg = <0xff800000 0x100>;
|
|
clocks = <&cru PCLK_WDT>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: sound@ff88b0000 {
|
|
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
|
|
reg = <0xff8b0000 0x10000>;
|
|
#sound-dai-cells = <0>;
|
|
clock-names = "hclk", "mclk";
|
|
clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
|
|
dmas = <&dmac_bus_s 3>;
|
|
dma-names = "tx";
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_tx>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s: i2s@ff890000 {
|
|
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0xff890000 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_hclk", "i2s_clk";
|
|
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vopb: vop@ff930000 {
|
|
compatible = "rockchip,rk3288-vop";
|
|
reg = <0xff930000 0x19c>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
power-domains = <&power RK3288_PD_VIO>;
|
|
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
|
|
reset-names = "axi", "ahb", "dclk";
|
|
iommus = <&vopb_mmu>;
|
|
status = "disabled";
|
|
|
|
vopb_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vopb_out_hdmi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&hdmi_in_vopb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
vopb_mmu: iommu@ff930300 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0xff930300 0x100>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vopb_mmu";
|
|
power-domains = <&power RK3288_PD_VIO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vopl: vop@ff940000 {
|
|
compatible = "rockchip,rk3288-vop";
|
|
reg = <0xff940000 0x19c>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
power-domains = <&power RK3288_PD_VIO>;
|
|
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
|
|
reset-names = "axi", "ahb", "dclk";
|
|
iommus = <&vopl_mmu>;
|
|
status = "disabled";
|
|
|
|
vopl_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vopl_out_hdmi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&hdmi_in_vopl>;
|
|
};
|
|
};
|
|
};
|
|
|
|
vopl_mmu: iommu@ff940300 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0xff940300 0x100>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vopl_mmu";
|
|
power-domains = <&power RK3288_PD_VIO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@ff980000 {
|
|
compatible = "rockchip,rk3288-dw-hdmi";
|
|
reg = <0xff980000 0x20000>;
|
|
reg-io-width = <4>;
|
|
rockchip,grf = <&grf>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
|
clock-names = "iahb", "isfr";
|
|
power-domains = <&power RK3288_PD_VIO>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
hdmi_in: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
hdmi_in_vopb: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vopb_out_hdmi>;
|
|
};
|
|
hdmi_in_vopl: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&vopl_out_hdmi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@ffc01000 {
|
|
compatible = "arm,gic-400";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
|
|
reg = <0xffc01000 0x1000>,
|
|
<0xffc02000 0x1000>,
|
|
<0xffc04000 0x2000>,
|
|
<0xffc06000 0x2000>;
|
|
interrupts = <GIC_PPI 9 0xf04>;
|
|
};
|
|
|
|
usbphy: phy {
|
|
compatible = "rockchip,rk3288-usb-phy";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
usbphy0: usb-phy0 {
|
|
#phy-cells = <0>;
|
|
reg = <0x320>;
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
|
clock-names = "phyclk";
|
|
};
|
|
|
|
usbphy1: usb-phy1 {
|
|
#phy-cells = <0>;
|
|
reg = <0x334>;
|
|
clocks = <&cru SCLK_OTGPHY1>;
|
|
clock-names = "phyclk";
|
|
};
|
|
|
|
usbphy2: usb-phy2 {
|
|
#phy-cells = <0>;
|
|
reg = <0x348>;
|
|
clocks = <&cru SCLK_OTGPHY2>;
|
|
clock-names = "phyclk";
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3288-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmu>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff750000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff750000 0x100>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff780000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff780000 0x100>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff790000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff790000 0x100>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff7a0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7a0000 0x100>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio4@ff7b0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7b0000 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio5@ff7c0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7c0000 0x100>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO5>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio6@ff7d0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7d0000 0x100>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio7@ff7e0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7e0000 0x100>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO7>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio8: gpio8@ff7f0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff7f0000 0x100>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO8>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
hdmi {
|
|
hdmi_ddc: hdmi-ddc {
|
|
rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
|
|
<7 20 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
sleep {
|
|
global_pwroff: global-pwroff {
|
|
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
ddrio_pwroff: ddrio-pwroff {
|
|
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
ddr0_retention: ddr0-retention {
|
|
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
ddr1_retention: ddr1-retention {
|
|
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 16 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<8 5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<7 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<7 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_bus: i2s0-bus {
|
|
rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 3 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<6 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_cd: sdmcc-cd {
|
|
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 17 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 18 RK_FUNC_1 &pcfg_pull_up>,
|
|
<6 19 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdio0 {
|
|
sdio0_bus1: sdio0-bus1 {
|
|
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 21 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 22 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 23 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio0_cd: sdio0-cd {
|
|
rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_wp: sdio0-wp {
|
|
rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_pwr: sdio0-pwr {
|
|
rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bkpwr: sdio0-bkpwr {
|
|
rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_int: sdio0-int {
|
|
rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdio1 {
|
|
sdio1_bus1: sdio1-bus1 {
|
|
rockchip,pins = <3 24 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_bus4: sdio1-bus4 {
|
|
rockchip,pins = <3 24 4 &pcfg_pull_up>,
|
|
<3 25 4 &pcfg_pull_up>,
|
|
<3 26 4 &pcfg_pull_up>,
|
|
<3 27 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_cd: sdio1-cd {
|
|
rockchip,pins = <3 28 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_wp: sdio1-wp {
|
|
rockchip,pins = <3 29 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_bkpwr: sdio1-bkpwr {
|
|
rockchip,pins = <3 30 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_int: sdio1-int {
|
|
rockchip,pins = <3 31 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_cmd: sdio1-cmd {
|
|
rockchip,pins = <4 6 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio1_clk: sdio1-clk {
|
|
rockchip,pins = <4 7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio1_pwr: sdio1-pwr {
|
|
rockchip,pins = <4 9 4 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_pwr: emmc-pwr {
|
|
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 3 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 3 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 4 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 5 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 6 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 7 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_cs1: spi2-cs1 {
|
|
rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
|
|
<5 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
|
|
<7 23 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
|
|
<7 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins = <5 12 3 &pcfg_pull_up>,
|
|
<5 13 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_cts: uart4-cts {
|
|
rockchip,pins = <5 14 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart4_rts: uart4-rts {
|
|
rockchip,pins = <5 15 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_out: otp-out {
|
|
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <7 22 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <7 23 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <3 30 3 &pcfg_pull_none>,
|
|
<3 31 3 &pcfg_pull_none>,
|
|
<3 26 3 &pcfg_pull_none>,
|
|
<3 27 3 &pcfg_pull_none>,
|
|
<3 28 3 &pcfg_pull_none_12ma>,
|
|
<3 29 3 &pcfg_pull_none_12ma>,
|
|
<3 24 3 &pcfg_pull_none_12ma>,
|
|
<3 25 3 &pcfg_pull_none_12ma>,
|
|
<4 0 3 &pcfg_pull_none>,
|
|
<4 5 3 &pcfg_pull_none>,
|
|
<4 6 3 &pcfg_pull_none>,
|
|
<4 9 3 &pcfg_pull_none_12ma>,
|
|
<4 4 3 &pcfg_pull_none_12ma>,
|
|
<4 1 3 &pcfg_pull_none>,
|
|
<4 3 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <3 30 3 &pcfg_pull_none>,
|
|
<3 31 3 &pcfg_pull_none>,
|
|
<3 28 3 &pcfg_pull_none>,
|
|
<3 29 3 &pcfg_pull_none>,
|
|
<4 0 3 &pcfg_pull_none>,
|
|
<4 5 3 &pcfg_pull_none>,
|
|
<4 4 3 &pcfg_pull_none>,
|
|
<4 1 3 &pcfg_pull_none>,
|
|
<4 2 3 &pcfg_pull_none>,
|
|
<4 3 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|