Eric Yang a39a581669 drm/amd/display: fix inputting clk lvl into dml for RN ... [Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-06 15:04:37 -05:00
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acp	drm/amdgpu: fix license on Kconfig and Makefiles	2019-12-11 15:22:08 -05:00
amdgpu	drm/amdgpu: move xgmi init/fini to xgmi_add/remove_device call (v2)	2020-02-06 15:04:36 -05:00
amdkfd	drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS mode	2020-02-04 10:32:41 -05:00
display	drm/amd/display: fix inputting clk lvl into dml for RN	2020-02-06 15:04:37 -05:00
include	drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus	2020-01-30 17:15:27 -05:00
powerplay	drm/amdgpu: update default voltage for boot od table for navi1x	2020-02-04 23:30:38 -05:00