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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Interrupt Control Unit
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*/
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#ifndef __ASM_MACH_ICU_H
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#define __ASM_MACH_ICU_H
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#include "addr-map.h"
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#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
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#define ICU_REG(x) (ICU_VIRT_BASE + (x))
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#define ICU_INT_CONF(n) ICU_REG((n) << 2)
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#define ICU_INT_CONF_MASK (0xf)
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/************ PXA168/PXA910 (MMP) *********************/
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#define ICU_INT_CONF_AP_INT (1 << 6)
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#define ICU_INT_CONF_CP_INT (1 << 5)
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#define ICU_INT_CONF_IRQ (1 << 4)
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#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
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#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
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#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
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#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
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#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
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/************************** MMP2 ***********************/
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/*
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* IRQ0/FIQ0 is routed to SP IRQ/FIQ.
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* IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
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*/
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#define ICU_INT_ROUTE_SP_IRQ (1 << 4)
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#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
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#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
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#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
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#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
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#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
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#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144)
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#define MMP2_ICU_INT4_STATUS ICU_REG(0x150)
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#define MMP2_ICU_INT5_STATUS ICU_REG(0x154)
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#define MMP2_ICU_INT17_STATUS ICU_REG(0x158)
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#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c)
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#define MMP2_ICU_INT51_STATUS ICU_REG(0x160)
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#define MMP2_ICU_INT4_MASK ICU_REG(0x168)
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#define MMP2_ICU_INT5_MASK ICU_REG(0x16C)
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#define MMP2_ICU_INT17_MASK ICU_REG(0x170)
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#define MMP2_ICU_INT35_MASK ICU_REG(0x174)
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#define MMP2_ICU_INT51_MASK ICU_REG(0x178)
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#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100)
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#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104)
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#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108)
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#define MMP2_ICU_INVERT ICU_REG(0x164)
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#define MMP2_ICU_INV_PMIC (1 << 0)
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#define MMP2_ICU_INV_PERF (1 << 1)
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#define MMP2_ICU_INV_COMMTX (1 << 2)
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#define MMP2_ICU_INV_COMMRX (1 << 3)
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#endif /* __ASM_MACH_ICU_H */
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