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27e154b2b6
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
49 lines
1.4 KiB
C
49 lines
1.4 KiB
C
/*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7791 CPG Core Clocks */
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#define R8A7791_CLK_Z 0
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#define R8A7791_CLK_ZG 1
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#define R8A7791_CLK_ZTR 2
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#define R8A7791_CLK_ZTRD2 3
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#define R8A7791_CLK_ZT 4
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#define R8A7791_CLK_ZX 5
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#define R8A7791_CLK_ZS 6
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#define R8A7791_CLK_HP 7
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#define R8A7791_CLK_I 8
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#define R8A7791_CLK_B 9
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#define R8A7791_CLK_LB 10
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#define R8A7791_CLK_P 11
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#define R8A7791_CLK_CL 12
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#define R8A7791_CLK_M2 13
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#define R8A7791_CLK_ADSP 14
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#define R8A7791_CLK_ZB3 15
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#define R8A7791_CLK_ZB3D2 16
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#define R8A7791_CLK_DDR 17
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#define R8A7791_CLK_SDH 18
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#define R8A7791_CLK_SD0 19
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#define R8A7791_CLK_SD2 20
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#define R8A7791_CLK_SD3 21
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#define R8A7791_CLK_MMC0 22
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#define R8A7791_CLK_MP 23
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#define R8A7791_CLK_SSP 24
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#define R8A7791_CLK_SSPRS 25
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#define R8A7791_CLK_QSPI 26
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#define R8A7791_CLK_CP 27
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#define R8A7791_CLK_RCAN 28
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#define R8A7791_CLK_R 29
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#define R8A7791_CLK_OSC 30
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#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
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