mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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68e2f64ee4
This adds all the OSD configuration plumbing to support the AFBC decoders path to display of the OSD1 plane. The Amlogic GXM and G12A AFBC decoders are integrated very differently. The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. On the other side, the Amlogic G12A AFBC decoder seems to be an external IP that emit pixels on an AXI master hooked to a "Mali Unpack" block feeding the OSD1 VIU pixel input. This uses a weird "0x1000000" internal HW physical address on both sides to transfer the pixels. For Amlogic GXM, the supported pixel formats are the same as the normal linear OSD1 mode. On the other side, Amlogic added support for all AFBC v1.2 formats for the G12A AFBC integration. For simplicity, we stick to the already supported formats for now. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-7-narmstrong@baylibre.com
157 lines
3.6 KiB
C
157 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __MESON_DRV_H
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#define __MESON_DRV_H
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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struct drm_crtc;
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struct drm_device;
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struct drm_plane;
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struct meson_drm;
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struct meson_afbcd_ops;
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enum vpu_compatible {
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VPU_COMPATIBLE_GXBB = 0,
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VPU_COMPATIBLE_GXL = 1,
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VPU_COMPATIBLE_GXM = 2,
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VPU_COMPATIBLE_G12A = 3,
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};
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struct meson_drm_match_data {
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enum vpu_compatible compat;
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struct meson_afbcd_ops *afbcd_ops;
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};
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struct meson_drm {
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struct device *dev;
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enum vpu_compatible compat;
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void __iomem *io_base;
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struct regmap *hhi;
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int vsync_irq;
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struct meson_canvas *canvas;
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u8 canvas_id_osd1;
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u8 canvas_id_vd1_0;
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u8 canvas_id_vd1_1;
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u8 canvas_id_vd1_2;
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struct drm_device *drm;
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struct drm_crtc *crtc;
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struct drm_plane *primary_plane;
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struct drm_plane *overlay_plane;
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/* Components Data */
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struct {
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bool osd1_enabled;
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bool osd1_interlace;
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bool osd1_commit;
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bool osd1_afbcd;
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uint32_t osd1_ctrl_stat;
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uint32_t osd1_ctrl_stat2;
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uint32_t osd1_blk0_cfg[5];
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uint32_t osd1_blk1_cfg4;
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uint32_t osd1_blk2_cfg4;
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uint32_t osd1_addr;
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uint32_t osd1_stride;
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uint32_t osd1_height;
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uint32_t osd1_width;
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uint32_t osd_sc_ctrl0;
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uint32_t osd_sc_i_wh_m1;
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uint32_t osd_sc_o_h_start_end;
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uint32_t osd_sc_o_v_start_end;
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uint32_t osd_sc_v_ini_phase;
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uint32_t osd_sc_v_phase_step;
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uint32_t osd_sc_h_ini_phase;
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uint32_t osd_sc_h_phase_step;
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uint32_t osd_sc_h_ctrl0;
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uint32_t osd_sc_v_ctrl0;
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uint32_t osd_blend_din0_scope_h;
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uint32_t osd_blend_din0_scope_v;
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uint32_t osb_blend0_size;
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uint32_t osb_blend1_size;
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bool vd1_enabled;
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bool vd1_commit;
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unsigned int vd1_planes;
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uint32_t vd1_if0_gen_reg;
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uint32_t vd1_if0_luma_x0;
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uint32_t vd1_if0_luma_y0;
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uint32_t vd1_if0_chroma_x0;
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uint32_t vd1_if0_chroma_y0;
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uint32_t vd1_if0_repeat_loop;
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uint32_t vd1_if0_luma0_rpt_pat;
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uint32_t vd1_if0_chroma0_rpt_pat;
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uint32_t vd1_range_map_y;
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uint32_t vd1_range_map_cb;
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uint32_t vd1_range_map_cr;
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uint32_t viu_vd1_fmt_w;
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uint32_t vd1_if0_canvas0;
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uint32_t vd1_if0_gen_reg2;
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uint32_t viu_vd1_fmt_ctrl;
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uint32_t vd1_addr0;
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uint32_t vd1_addr1;
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uint32_t vd1_addr2;
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uint32_t vd1_stride0;
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uint32_t vd1_stride1;
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uint32_t vd1_stride2;
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uint32_t vd1_height0;
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uint32_t vd1_height1;
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uint32_t vd1_height2;
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uint32_t vpp_pic_in_height;
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uint32_t vpp_postblend_vd1_h_start_end;
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uint32_t vpp_postblend_vd1_v_start_end;
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uint32_t vpp_hsc_region12_startp;
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uint32_t vpp_hsc_region34_startp;
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uint32_t vpp_hsc_region4_endp;
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uint32_t vpp_hsc_start_phase_step;
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uint32_t vpp_hsc_region1_phase_slope;
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uint32_t vpp_hsc_region3_phase_slope;
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uint32_t vpp_line_in_length;
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uint32_t vpp_preblend_h_size;
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uint32_t vpp_vsc_region12_startp;
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uint32_t vpp_vsc_region34_startp;
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uint32_t vpp_vsc_region4_endp;
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uint32_t vpp_vsc_start_phase_step;
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uint32_t vpp_vsc_ini_phase;
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uint32_t vpp_vsc_phase_ctrl;
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uint32_t vpp_hsc_phase_ctrl;
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uint32_t vpp_blend_vd2_h_start_end;
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uint32_t vpp_blend_vd2_v_start_end;
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} viu;
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struct {
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unsigned int current_mode;
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bool hdmi_repeat;
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bool venc_repeat;
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bool hdmi_use_enci;
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} venc;
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struct {
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dma_addr_t addr_phys;
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uint32_t *addr;
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unsigned int offset;
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} rdma;
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struct {
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struct meson_afbcd_ops *ops;
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u64 modifier;
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u32 format;
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} afbcd;
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};
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static inline int meson_vpu_is_compatible(struct meson_drm *priv,
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enum vpu_compatible family)
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{
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return priv->compat == family;
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}
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#endif /* __MESON_DRV_H */
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