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f3a02ecebe
TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is reliable and the frequency is known (provided by HW). On these platforms PIT/HPET is generally not available so calibration won't work at all and there is no other clocksource to act as a watchdog for the TSC, so we have no other choice than to trust it. Set both X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_RELIABLE flags to make sure the calibration is skipped and no watchdog is required. Signed-off-by: Bin Gao <bin.gao@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1479241644-234277-5-git-send-email-bin.gao@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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| .. | ||
| atom | ||
| ce4100 | ||
| efi | ||
| geode | ||
| goldfish | ||
| intel | ||
| intel-mid | ||
| intel-quark | ||
| iris | ||
| mellanox | ||
| olpc | ||
| scx200 | ||
| sfi | ||
| ts5500 | ||
| uv | ||
| Makefile | ||