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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a34caf78f2
Allows most of the code to be shared between nv84/nvc0 implementations, and paves the way for doing emit/sync on non-VRAM buffers (multi-gpu, dma-buf). Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
123 lines
3.6 KiB
C
123 lines
3.6 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/object.h>
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#include <core/client.h>
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#include <core/class.h>
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#include <engine/fifo.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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#include "nv50_display.h"
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static int
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nvc0_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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struct nv84_fence_chan *fctx = chan->fence;
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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u64 addr = fctx->vma.offset + fifo->chid * 16;
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int ret;
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ret = RING_SPACE(chan, 6);
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if (ret == 0) {
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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OUT_RING (chan, 0x00000000);
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FIRE_RING (chan);
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}
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return ret;
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}
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static int
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nvc0_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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struct nv84_fence_chan *fctx = chan->fence;
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struct nouveau_fifo_chan *fifo = (void *)prev->object;
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u64 addr = fctx->vma.offset + fifo->chid * 16;
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int ret;
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ret = RING_SPACE(chan, 5);
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if (ret == 0) {
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
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NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
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FIRE_RING (chan);
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}
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return ret;
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}
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int
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nvc0_fence_create(struct nouveau_drm *drm)
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{
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struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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struct nv84_fence_priv *priv;
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int ret;
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.dtor = nv84_fence_destroy;
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priv->base.suspend = nv84_fence_suspend;
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priv->base.resume = nv84_fence_resume;
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priv->base.context_new = nv84_fence_context_new;
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priv->base.context_del = nv84_fence_context_del;
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priv->base.emit = nvc0_fence_emit;
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priv->base.sync = nvc0_fence_sync;
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priv->base.read = nv84_fence_read;
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init_waitqueue_head(&priv->base.waiting);
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priv->base.uevent = true;
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ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
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TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
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if (ret == 0) {
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ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
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if (ret == 0) {
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ret = nouveau_bo_map(priv->bo);
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if (ret)
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nouveau_bo_unpin(priv->bo);
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}
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if (ret)
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nouveau_bo_ref(NULL, &priv->bo);
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}
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if (ret)
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nv84_fence_destroy(drm);
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return ret;
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}
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