mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 21:42:20 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
108 lines
1.8 KiB
ArmAsm
108 lines
1.8 KiB
ArmAsm
/*
|
|
* linux/arch/arm26/lib/io-readsw.S
|
|
*
|
|
* Copyright (C) 1995-2000 Russell King
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#include <linux/linkage.h>
|
|
#include <asm/assembler.h>
|
|
#include <asm/hardware.h>
|
|
|
|
.insw_bad_alignment:
|
|
adr r0, .insw_bad_align_msg
|
|
mov r2, lr
|
|
b panic
|
|
.insw_bad_align_msg:
|
|
.asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
|
|
.align
|
|
|
|
.insw_align: tst r1, #1
|
|
bne .insw_bad_alignment
|
|
|
|
ldr r3, [r0]
|
|
strb r3, [r1], #1
|
|
mov r3, r3, lsr #8
|
|
strb r3, [r1], #1
|
|
|
|
subs r2, r2, #1
|
|
RETINSTR(moveq, pc, lr)
|
|
|
|
ENTRY(__raw_readsw)
|
|
teq r2, #0 @ do we have to check for the zero len?
|
|
moveq pc, lr
|
|
tst r1, #3
|
|
bne .insw_align
|
|
|
|
.insw_aligned: mov ip, #0xff
|
|
orr ip, ip, ip, lsl #8
|
|
stmfd sp!, {r4, r5, r6, lr}
|
|
|
|
subs r2, r2, #8
|
|
bmi .no_insw_8
|
|
|
|
.insw_8_lp: ldr r3, [r0]
|
|
and r3, r3, ip
|
|
ldr r4, [r0]
|
|
orr r3, r3, r4, lsl #16
|
|
|
|
ldr r4, [r0]
|
|
and r4, r4, ip
|
|
ldr r5, [r0]
|
|
orr r4, r4, r5, lsl #16
|
|
|
|
ldr r5, [r0]
|
|
and r5, r5, ip
|
|
ldr r6, [r0]
|
|
orr r5, r5, r6, lsl #16
|
|
|
|
ldr r6, [r0]
|
|
and r6, r6, ip
|
|
ldr lr, [r0]
|
|
orr r6, r6, lr, lsl #16
|
|
|
|
stmia r1!, {r3 - r6}
|
|
|
|
subs r2, r2, #8
|
|
bpl .insw_8_lp
|
|
|
|
tst r2, #7
|
|
LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
|
|
|
|
.no_insw_8: tst r2, #4
|
|
beq .no_insw_4
|
|
|
|
ldr r3, [r0]
|
|
and r3, r3, ip
|
|
ldr r4, [r0]
|
|
orr r3, r3, r4, lsl #16
|
|
|
|
ldr r4, [r0]
|
|
and r4, r4, ip
|
|
ldr r5, [r0]
|
|
orr r4, r4, r5, lsl #16
|
|
|
|
stmia r1!, {r3, r4}
|
|
|
|
.no_insw_4: tst r2, #2
|
|
beq .no_insw_2
|
|
|
|
ldr r3, [r0]
|
|
and r3, r3, ip
|
|
ldr r4, [r0]
|
|
orr r3, r3, r4, lsl #16
|
|
|
|
str r3, [r1], #4
|
|
|
|
.no_insw_2: tst r2, #1
|
|
ldrne r3, [r0]
|
|
strneb r3, [r1], #1
|
|
movne r3, r3, lsr #8
|
|
strneb r3, [r1]
|
|
|
|
LOADREGS(fd, sp!, {r4, r5, r6, pc})
|
|
|
|
|