Manasi Navare a311b0b5d2 drm/i915/dp: Configure Display stream splitter registers during DSC enable ... Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v4: * Remove redundant comment (Ville) v3: * Use cpu_transcoder instead of encoder->type (Ville) v2: * Rebase (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-11-manasi.d.navare@intel.com		2018-11-29 12:30:50 -08:00
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drm	drm/i915/dp: Configure Display stream splitter registers during DSC enable	2018-11-29 12:30:50 -08:00
host1x
ipu-v3
vga	drm-misc-next for v4.21, part 1:	2018-11-19 10:40:33 +10:00
Makefile