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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dafb9c70ab
On Exynos SoCs the FIMC IP allows to configure globally the alpha component of all pixels for V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB555 and V4L2_PIX_FMT_RGB444 image formats. This patch adds a v4l2 control in order to let the applications control the alpha component value. The alpha value range depends on the pixel format, for RGB32 it's 0..255 (8-bits), for RGB555 - 0..1 (1-bit) and for RGB444 - 0..15 (4-bits). The v4l2 control range is always 0..255 and the alpha component data width is determined by currently set format on the V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE buffer queue. The applications need to match the alpha channel value range and the pixel format since the driver will clamp the alpha component. Depending on fourcc the valid alpha bits are: - V4L2_PIX_FMT_RGB555 [0] - V4L2_PIX_FMT_RGB444 [3:0] - V4L2_PIX_FMT_RGB32 [7:0] When switching to a pixel format with smaller alpha component width the currently set alpha value will be clamped to maximum value valid for current format. When switching to a format with wider alpha the alpha value remains unchanged. The variant description data structure is extended with a new entry so an additional control is created only where really supported by the hardware. V4L2_PIX_FMT_RGB555 and V4L2_PIX_FMT_RGB444 formats are only valid for V4L2_BUF_TYPE_VIDEO_CAPTURE buffer queue. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
302 lines
11 KiB
C
302 lines
11 KiB
C
/*
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* Register definition file for Samsung Camera Interface (FIMC) driver
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*
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* Copyright (c) 2010 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef REGS_FIMC_H_
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#define REGS_FIMC_H_
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/* Input source format */
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#define S5P_CISRCFMT 0x00
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#define S5P_CISRCFMT_ITU601_8BIT (1 << 31)
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#define S5P_CISRCFMT_ITU601_16BIT (1 << 29)
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#define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14)
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#define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14)
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#define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14)
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#define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14)
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#define S5P_CISRCFMT_HSIZE(x) ((x) << 16)
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#define S5P_CISRCFMT_VSIZE(x) ((x) << 0)
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/* Window offset */
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#define S5P_CIWDOFST 0x04
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#define S5P_CIWDOFST_OFF_EN (1 << 31)
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#define S5P_CIWDOFST_CLROVFIY (1 << 30)
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#define S5P_CIWDOFST_CLROVRLB (1 << 29)
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#define S5P_CIWDOFST_HOROFF_MASK (0x7ff << 16)
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#define S5P_CIWDOFST_CLROVFICB (1 << 15)
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#define S5P_CIWDOFST_CLROVFICR (1 << 14)
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#define S5P_CIWDOFST_HOROFF(x) ((x) << 16)
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#define S5P_CIWDOFST_VEROFF(x) ((x) << 0)
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#define S5P_CIWDOFST_VEROFF_MASK (0xfff << 0)
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/* Global control */
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#define S5P_CIGCTRL 0x08
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#define S5P_CIGCTRL_SWRST (1 << 31)
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#define S5P_CIGCTRL_CAMRST_A (1 << 30)
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#define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29)
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#define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27)
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#define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
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#define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
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#define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27)
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#define S5P_CIGCTRL_TESTPAT_MASK (3 << 27)
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#define S5P_CIGCTRL_TESTPAT_SHIFT (27)
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#define S5P_CIGCTRL_INVPOLPCLK (1 << 26)
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#define S5P_CIGCTRL_INVPOLVSYNC (1 << 25)
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#define S5P_CIGCTRL_INVPOLHREF (1 << 24)
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#define S5P_CIGCTRL_IRQ_OVFEN (1 << 22)
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#define S5P_CIGCTRL_HREF_MASK (1 << 21)
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#define S5P_CIGCTRL_IRQ_LEVEL (1 << 20)
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#define S5P_CIGCTRL_IRQ_CLR (1 << 19)
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#define S5P_CIGCTRL_IRQ_ENABLE (1 << 16)
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#define S5P_CIGCTRL_SHDW_DISABLE (1 << 12)
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#define S5P_CIGCTRL_CAM_JPEG (1 << 8)
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#define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7)
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#define S5P_CIGCTRL_CAMIF_SELWB (1 << 6)
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/* 0 - ITU601; 1 - ITU709 */
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#define S5P_CIGCTRL_CSC_ITU601_709 (1 << 5)
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#define S5P_CIGCTRL_INVPOLHSYNC (1 << 4)
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#define S5P_CIGCTRL_SELCAM_MIPI (1 << 3)
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#define S5P_CIGCTRL_INVPOLFIELD (1 << 1)
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#define S5P_CIGCTRL_INTERLACE (1 << 0)
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/* Window offset 2 */
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#define S5P_CIWDOFST2 0x14
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#define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16)
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#define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0)
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#define S5P_CIWDOFST2_HOROFF(x) ((x) << 16)
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#define S5P_CIWDOFST2_VEROFF(x) ((x) << 0)
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/* Output DMA Y/Cb/Cr plane start addresses */
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#define S5P_CIOYSA(n) (0x18 + (n) * 4)
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#define S5P_CIOCBSA(n) (0x28 + (n) * 4)
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#define S5P_CIOCRSA(n) (0x38 + (n) * 4)
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/* Target image format */
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#define S5P_CITRGFMT 0x48
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#define S5P_CITRGFMT_INROT90 (1 << 31)
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#define S5P_CITRGFMT_YCBCR420 (0 << 29)
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#define S5P_CITRGFMT_YCBCR422 (1 << 29)
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#define S5P_CITRGFMT_YCBCR422_1P (2 << 29)
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#define S5P_CITRGFMT_RGB (3 << 29)
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#define S5P_CITRGFMT_FMT_MASK (3 << 29)
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#define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16)
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#define S5P_CITRGFMT_FLIP_SHIFT (14)
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#define S5P_CITRGFMT_FLIP_NORMAL (0 << 14)
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#define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14)
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#define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
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#define S5P_CITRGFMT_FLIP_180 (3 << 14)
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#define S5P_CITRGFMT_FLIP_MASK (3 << 14)
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#define S5P_CITRGFMT_OUTROT90 (1 << 13)
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#define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0)
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#define S5P_CITRGFMT_HSIZE(x) ((x) << 16)
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#define S5P_CITRGFMT_VSIZE(x) ((x) << 0)
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/* Output DMA control */
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#define S5P_CIOCTRL 0x4c
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#define S5P_CIOCTRL_ORDER422_MASK (3 << 0)
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#define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0)
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#define S5P_CIOCTRL_ORDER422_CBYCRY (1 << 0)
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#define S5P_CIOCTRL_ORDER422_YCRYCB (2 << 0)
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#define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0)
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#define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
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#define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3)
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#define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3)
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#define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
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#define S5P_CIOCTRL_ALPHA_OUT_MASK (0xff << 4)
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#define S5P_CIOCTRL_RGB16FMT_MASK (3 << 16)
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#define S5P_CIOCTRL_RGB565 (0 << 16)
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#define S5P_CIOCTRL_ARGB1555 (1 << 16)
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#define S5P_CIOCTRL_ARGB4444 (2 << 16)
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#define S5P_CIOCTRL_ORDER2P_SHIFT (24)
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#define S5P_CIOCTRL_ORDER2P_MASK (3 << 24)
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#define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
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/* Pre-scaler control 1 */
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#define S5P_CISCPRERATIO 0x50
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#define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
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#define S5P_CISCPRERATIO_HOR(x) ((x) << 16)
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#define S5P_CISCPRERATIO_VER(x) ((x) << 0)
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#define S5P_CISCPREDST 0x54
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#define S5P_CISCPREDST_WIDTH(x) ((x) << 16)
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#define S5P_CISCPREDST_HEIGHT(x) ((x) << 0)
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/* Main scaler control */
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#define S5P_CISCCTRL 0x58
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#define S5P_CISCCTRL_SCALERBYPASS (1 << 31)
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#define S5P_CISCCTRL_SCALEUP_H (1 << 30)
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#define S5P_CISCCTRL_SCALEUP_V (1 << 29)
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#define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28)
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#define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27)
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#define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
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#define S5P_CISCCTRL_INTERLACE (1 << 25)
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#define S5P_CISCCTRL_SCALERSTART (1 << 15)
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#define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
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#define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
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#define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
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#define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13)
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#define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
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#define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
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#define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
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#define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
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#define S5P_CISCCTRL_RGB_EXT (1 << 10)
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#define S5P_CISCCTRL_ONE2ONE (1 << 9)
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#define S5P_CISCCTRL_MHRATIO(x) ((x) << 16)
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#define S5P_CISCCTRL_MVRATIO(x) ((x) << 0)
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#define S5P_CISCCTRL_MHRATIO_MASK (0x1ff << 16)
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#define S5P_CISCCTRL_MVRATIO_MASK (0x1ff << 0)
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#define S5P_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16)
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#define S5P_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0)
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/* Target area */
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#define S5P_CITAREA 0x5c
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#define S5P_CITAREA_MASK 0x0fffffff
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/* General status */
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#define S5P_CISTATUS 0x64
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#define S5P_CISTATUS_OVFIY (1 << 31)
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#define S5P_CISTATUS_OVFICB (1 << 30)
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#define S5P_CISTATUS_OVFICR (1 << 29)
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#define S5P_CISTATUS_VSYNC (1 << 28)
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#define S5P_CISTATUS_FRAMECNT_MASK (3 << 26)
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#define S5P_CISTATUS_FRAMECNT_SHIFT 26
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#define S5P_CISTATUS_WINOFF_EN (1 << 25)
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#define S5P_CISTATUS_IMGCPT_EN (1 << 22)
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#define S5P_CISTATUS_IMGCPT_SCEN (1 << 21)
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#define S5P_CISTATUS_VSYNC_A (1 << 20)
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#define S5P_CISTATUS_VSYNC_B (1 << 19)
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#define S5P_CISTATUS_OVRLB (1 << 18)
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#define S5P_CISTATUS_FRAME_END (1 << 17)
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#define S5P_CISTATUS_LASTCAPT_END (1 << 16)
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#define S5P_CISTATUS_VVALID_A (1 << 15)
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#define S5P_CISTATUS_VVALID_B (1 << 14)
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/* Indexes to the last and the currently processed buffer. */
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#define S5P_CISTATUS2 0x68
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/* Image capture control */
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#define S5P_CIIMGCPT 0xc0
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#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
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#define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30)
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#define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
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#define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
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/* Frame capture sequence */
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#define S5P_CICPTSEQ 0xc4
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/* Image effect */
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#define S5P_CIIMGEFF 0xd0
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#define S5P_CIIMGEFF_IE_ENABLE (1 << 30)
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#define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29)
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#define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29)
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#define S5P_CIIMGEFF_FIN_BYPASS (0 << 26)
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#define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26)
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#define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26)
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#define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
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#define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26)
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#define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
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#define S5P_CIIMGEFF_FIN_MASK (7 << 26)
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#define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
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#define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13)
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#define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0)
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/* Input DMA Y/Cb/Cr plane start address 0/1 */
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#define S5P_CIIYSA(n) (0xd4 + (n) * 0x70)
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#define S5P_CIICBSA(n) (0xd8 + (n) * 0x70)
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#define S5P_CIICRSA(n) (0xdc + (n) * 0x70)
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/* Real input DMA image size */
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#define S5P_CIREAL_ISIZE 0xf8
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#define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
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#define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
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#define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
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#define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
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/* Input DMA control */
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#define S5P_MSCTRL 0xfc
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#define S5P_MSCTRL_IN_BURST_COUNT_MASK (0xF << 24)
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#define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
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#define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16
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#define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15)
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#define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15)
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#define S5P_MSCTRL_C_INT_IN_MASK (1 << 15)
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#define S5P_MSCTRL_FLIP_SHIFT 13
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#define S5P_MSCTRL_FLIP_MASK (3 << 13)
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#define S5P_MSCTRL_FLIP_NORMAL (0 << 13)
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#define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
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#define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
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#define S5P_MSCTRL_FLIP_180 (3 << 13)
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#define S5P_MSCTRL_FIFO_CTRL_FULL (1 << 12)
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#define S5P_MSCTRL_ORDER422_SHIFT 4
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#define S5P_MSCTRL_ORDER422_YCBYCR (0 << 4)
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#define S5P_MSCTRL_ORDER422_CBYCRY (1 << 4)
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#define S5P_MSCTRL_ORDER422_YCRYCB (2 << 4)
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#define S5P_MSCTRL_ORDER422_CRYCBY (3 << 4)
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#define S5P_MSCTRL_ORDER422_MASK (3 << 4)
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#define S5P_MSCTRL_INPUT_EXTCAM (0 << 3)
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#define S5P_MSCTRL_INPUT_MEMORY (1 << 3)
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#define S5P_MSCTRL_INPUT_MASK (1 << 3)
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#define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
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#define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
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#define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
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#define S5P_MSCTRL_INFORMAT_RGB (3 << 1)
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#define S5P_MSCTRL_INFORMAT_MASK (3 << 1)
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#define S5P_MSCTRL_ENVID (1 << 0)
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#define S5P_MSCTRL_IN_BURST_COUNT(x) ((x) << 24)
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/* Output DMA Y/Cb/Cr offset */
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#define S5P_CIOYOFF 0x168
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#define S5P_CIOCBOFF 0x16c
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#define S5P_CIOCROFF 0x170
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/* Input DMA Y/Cb/Cr offset */
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#define S5P_CIIYOFF 0x174
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#define S5P_CIICBOFF 0x178
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#define S5P_CIICROFF 0x17c
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#define S5P_CIO_OFFS_VER(x) ((x) << 16)
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#define S5P_CIO_OFFS_HOR(x) ((x) << 0)
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/* Input DMA original image size */
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#define S5P_ORGISIZE 0x180
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/* Output DMA original image size */
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#define S5P_ORGOSIZE 0x184
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#define S5P_ORIG_SIZE_VER(x) ((x) << 16)
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#define S5P_ORIG_SIZE_HOR(x) ((x) << 0)
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/* Real output DMA image size (extension register) */
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#define S5P_CIEXTEN 0x188
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#define S5P_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10)
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#define S5P_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f)
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#define S5P_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10)
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#define S5P_CIEXTEN_MVRATIO_EXT_MASK 0x3f
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#define S5P_CIDMAPARAM 0x18c
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#define S5P_CIDMAPARAM_R_LINEAR (0 << 29)
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#define S5P_CIDMAPARAM_R_64X32 (3 << 29)
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#define S5P_CIDMAPARAM_W_LINEAR (0 << 13)
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#define S5P_CIDMAPARAM_W_64X32 (3 << 13)
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#define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
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/* MIPI CSI image format */
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#define S5P_CSIIMGFMT 0x194
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#define S5P_CSIIMGFMT_YCBCR422_8BIT 0x1e
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#define S5P_CSIIMGFMT_RAW8 0x2a
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#define S5P_CSIIMGFMT_RAW10 0x2b
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#define S5P_CSIIMGFMT_RAW12 0x2c
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/* User defined formats. x = 0...16. */
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#define S5P_CSIIMGFMT_USER(x) (0x30 + x - 1)
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/* Output frame buffer sequence mask */
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#define S5P_CIFCNTSEQ 0x1FC
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#endif /* REGS_FIMC_H_ */
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