mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 10:40:53 +07:00
9549b5ff00
The device type was stored in sec_pmic_dev state container twice: - unsigned long type (initialized from of_device_id or i2c_device_id) - int device_type (initialized as above or from board files when there is no DTS) The 'type' field was never used outside of probe so it can be safely removed. Change also the device_type in sec_pmic_dev and sec_platform_data to unsigned long to avoid any casts. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
405 lines
8.8 KiB
C
405 lines
8.8 KiB
C
/*
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* sec-irq.c
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*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/regmap.h>
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#include <linux/mfd/samsung/core.h>
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#include <linux/mfd/samsung/irq.h>
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#include <linux/mfd/samsung/s2mps11.h>
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#include <linux/mfd/samsung/s2mps14.h>
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#include <linux/mfd/samsung/s5m8763.h>
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#include <linux/mfd/samsung/s5m8767.h>
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static const struct regmap_irq s2mps11_irqs[] = {
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[S2MPS11_IRQ_PWRONF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONF_MASK,
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},
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[S2MPS11_IRQ_PWRONR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONR_MASK,
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},
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[S2MPS11_IRQ_JIGONBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBF_MASK,
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},
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[S2MPS11_IRQ_JIGONBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBR_MASK,
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},
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[S2MPS11_IRQ_ACOKBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBF_MASK,
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},
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[S2MPS11_IRQ_ACOKBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBR_MASK,
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},
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[S2MPS11_IRQ_PWRON1S] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRON1S_MASK,
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},
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[S2MPS11_IRQ_MRB] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_MRB_MASK,
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},
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[S2MPS11_IRQ_RTC60S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC60S_MASK,
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},
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[S2MPS11_IRQ_RTCA0] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA0_MASK,
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},
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[S2MPS11_IRQ_RTCA1] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA1_MASK,
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},
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[S2MPS11_IRQ_SMPL] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_SMPL_MASK,
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},
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[S2MPS11_IRQ_RTC1S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC1S_MASK,
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},
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[S2MPS11_IRQ_WTSR] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_WTSR_MASK,
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},
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[S2MPS11_IRQ_INT120C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT120C_MASK,
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},
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[S2MPS11_IRQ_INT140C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT140C_MASK,
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},
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};
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static const struct regmap_irq s2mps14_irqs[] = {
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[S2MPS14_IRQ_PWRONF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONF_MASK,
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},
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[S2MPS14_IRQ_PWRONR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONR_MASK,
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},
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[S2MPS14_IRQ_JIGONBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBF_MASK,
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},
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[S2MPS14_IRQ_JIGONBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBR_MASK,
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},
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[S2MPS14_IRQ_ACOKBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBF_MASK,
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},
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[S2MPS14_IRQ_ACOKBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBR_MASK,
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},
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[S2MPS14_IRQ_PWRON1S] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRON1S_MASK,
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},
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[S2MPS14_IRQ_MRB] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_MRB_MASK,
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},
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[S2MPS14_IRQ_RTC60S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC60S_MASK,
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},
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[S2MPS14_IRQ_RTCA1] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA1_MASK,
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},
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[S2MPS14_IRQ_RTCA0] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA0_MASK,
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},
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[S2MPS14_IRQ_SMPL] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_SMPL_MASK,
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},
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[S2MPS14_IRQ_RTC1S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC1S_MASK,
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},
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[S2MPS14_IRQ_WTSR] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_WTSR_MASK,
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},
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[S2MPS14_IRQ_INT120C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT120C_MASK,
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},
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[S2MPS14_IRQ_INT140C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT140C_MASK,
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},
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[S2MPS14_IRQ_TSD] = {
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.reg_offset = 2,
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.mask = S2MPS14_IRQ_TSD_MASK,
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},
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};
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static const struct regmap_irq s5m8767_irqs[] = {
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[S5M8767_IRQ_PWRR] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_PWRR_MASK,
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},
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[S5M8767_IRQ_PWRF] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_PWRF_MASK,
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},
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[S5M8767_IRQ_PWR1S] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_PWR1S_MASK,
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},
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[S5M8767_IRQ_JIGR] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_JIGR_MASK,
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},
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[S5M8767_IRQ_JIGF] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_JIGF_MASK,
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},
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[S5M8767_IRQ_LOWBAT2] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_LOWBAT2_MASK,
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},
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[S5M8767_IRQ_LOWBAT1] = {
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.reg_offset = 0,
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.mask = S5M8767_IRQ_LOWBAT1_MASK,
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},
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[S5M8767_IRQ_MRB] = {
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.reg_offset = 1,
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.mask = S5M8767_IRQ_MRB_MASK,
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},
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[S5M8767_IRQ_DVSOK2] = {
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.reg_offset = 1,
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.mask = S5M8767_IRQ_DVSOK2_MASK,
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},
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[S5M8767_IRQ_DVSOK3] = {
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.reg_offset = 1,
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.mask = S5M8767_IRQ_DVSOK3_MASK,
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},
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[S5M8767_IRQ_DVSOK4] = {
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.reg_offset = 1,
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.mask = S5M8767_IRQ_DVSOK4_MASK,
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},
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[S5M8767_IRQ_RTC60S] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_RTC60S_MASK,
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},
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[S5M8767_IRQ_RTCA1] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_RTCA1_MASK,
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},
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[S5M8767_IRQ_RTCA2] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_RTCA2_MASK,
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},
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[S5M8767_IRQ_SMPL] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_SMPL_MASK,
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},
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[S5M8767_IRQ_RTC1S] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_RTC1S_MASK,
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},
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[S5M8767_IRQ_WTSR] = {
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.reg_offset = 2,
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.mask = S5M8767_IRQ_WTSR_MASK,
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},
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};
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static const struct regmap_irq s5m8763_irqs[] = {
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[S5M8763_IRQ_DCINF] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_DCINF_MASK,
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},
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[S5M8763_IRQ_DCINR] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_DCINR_MASK,
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},
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[S5M8763_IRQ_JIGF] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_JIGF_MASK,
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},
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[S5M8763_IRQ_JIGR] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_JIGR_MASK,
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},
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[S5M8763_IRQ_PWRONF] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_PWRONF_MASK,
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},
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[S5M8763_IRQ_PWRONR] = {
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.reg_offset = 0,
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.mask = S5M8763_IRQ_PWRONR_MASK,
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},
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[S5M8763_IRQ_WTSREVNT] = {
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.reg_offset = 1,
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.mask = S5M8763_IRQ_WTSREVNT_MASK,
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},
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[S5M8763_IRQ_SMPLEVNT] = {
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.reg_offset = 1,
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.mask = S5M8763_IRQ_SMPLEVNT_MASK,
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},
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[S5M8763_IRQ_ALARM1] = {
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.reg_offset = 1,
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.mask = S5M8763_IRQ_ALARM1_MASK,
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},
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[S5M8763_IRQ_ALARM0] = {
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.reg_offset = 1,
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.mask = S5M8763_IRQ_ALARM0_MASK,
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},
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[S5M8763_IRQ_ONKEY1S] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_ONKEY1S_MASK,
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},
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[S5M8763_IRQ_TOPOFFR] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_TOPOFFR_MASK,
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},
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[S5M8763_IRQ_DCINOVPR] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_DCINOVPR_MASK,
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},
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[S5M8763_IRQ_CHGRSTF] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_CHGRSTF_MASK,
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},
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[S5M8763_IRQ_DONER] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_DONER_MASK,
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},
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[S5M8763_IRQ_CHGFAULT] = {
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.reg_offset = 2,
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.mask = S5M8763_IRQ_CHGFAULT_MASK,
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},
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[S5M8763_IRQ_LOBAT1] = {
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.reg_offset = 3,
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.mask = S5M8763_IRQ_LOBAT1_MASK,
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},
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[S5M8763_IRQ_LOBAT2] = {
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.reg_offset = 3,
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.mask = S5M8763_IRQ_LOBAT2_MASK,
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},
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};
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static const struct regmap_irq_chip s2mps11_irq_chip = {
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.name = "s2mps11",
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.irqs = s2mps11_irqs,
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.num_irqs = ARRAY_SIZE(s2mps11_irqs),
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.num_regs = 3,
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.status_base = S2MPS11_REG_INT1,
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.mask_base = S2MPS11_REG_INT1M,
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.ack_base = S2MPS11_REG_INT1,
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};
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static const struct regmap_irq_chip s2mps14_irq_chip = {
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.name = "s2mps14",
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.irqs = s2mps14_irqs,
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.num_irqs = ARRAY_SIZE(s2mps14_irqs),
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.num_regs = 3,
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.status_base = S2MPS14_REG_INT1,
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.mask_base = S2MPS14_REG_INT1M,
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.ack_base = S2MPS14_REG_INT1,
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};
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static const struct regmap_irq_chip s5m8767_irq_chip = {
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.name = "s5m8767",
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.irqs = s5m8767_irqs,
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.num_irqs = ARRAY_SIZE(s5m8767_irqs),
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.num_regs = 3,
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.status_base = S5M8767_REG_INT1,
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.mask_base = S5M8767_REG_INT1M,
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.ack_base = S5M8767_REG_INT1,
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};
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static const struct regmap_irq_chip s5m8763_irq_chip = {
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.name = "s5m8763",
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.irqs = s5m8763_irqs,
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.num_irqs = ARRAY_SIZE(s5m8763_irqs),
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.num_regs = 4,
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.status_base = S5M8763_REG_IRQ1,
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.mask_base = S5M8763_REG_IRQM1,
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.ack_base = S5M8763_REG_IRQ1,
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};
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int sec_irq_init(struct sec_pmic_dev *sec_pmic)
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{
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int ret = 0;
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int type = sec_pmic->device_type;
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if (!sec_pmic->irq) {
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dev_warn(sec_pmic->dev,
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"No interrupt specified, no interrupts\n");
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sec_pmic->irq_base = 0;
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return 0;
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}
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switch (type) {
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case S5M8763X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s5m8763_irq_chip,
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&sec_pmic->irq_data);
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break;
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case S5M8767X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s5m8767_irq_chip,
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&sec_pmic->irq_data);
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break;
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case S2MPS11X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s2mps11_irq_chip,
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&sec_pmic->irq_data);
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break;
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case S2MPS14X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s2mps14_irq_chip,
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&sec_pmic->irq_data);
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break;
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default:
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dev_err(sec_pmic->dev, "Unknown device type %lu\n",
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sec_pmic->device_type);
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return -EINVAL;
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}
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if (ret != 0) {
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dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void sec_irq_exit(struct sec_pmic_dev *sec_pmic)
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{
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regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data);
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}
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