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30b8e27e3b
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <wesley@sifive.com>:
999529edf5
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
This version includes several changes requested by Stephen Boyd
<sboyd@kernel.org>.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Wesley W. Terpstra <wesley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Megan Wachs <megan@sifive.com>
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
[sboyd@kernel.org: Fix some const and ARRAY_SIZE() issues, make makefile
only descend if CLK_SIFIVE=y]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
19 lines
444 B
Plaintext
19 lines
444 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menuconfig CLK_SIFIVE
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bool "SiFive SoC driver support"
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help
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SoC drivers for SiFive Linux-capable SoCs.
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if CLK_SIFIVE
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config CLK_SIFIVE_FU540_PRCI
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bool "PRCI driver for SiFive FU540 SoCs"
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select CLK_ANALOGBITS_WRPLL_CLN28HPC
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help
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Supports the Power Reset Clock interface (PRCI) IP block found in
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FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
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enable this driver.
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endif
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