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0eaeb070ed
irq need to update when gpu reset happens. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
104 lines
3.5 KiB
C
104 lines
3.5 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IRQ_H__
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#define __AMDGPU_IRQ_H__
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#include <linux/irqdomain.h>
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#include "amdgpu_ih.h"
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#define AMDGPU_MAX_IRQ_SRC_ID 0x100
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struct amdgpu_device;
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struct amdgpu_iv_entry;
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enum amdgpu_interrupt_state {
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AMDGPU_IRQ_STATE_DISABLE,
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AMDGPU_IRQ_STATE_ENABLE,
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};
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struct amdgpu_irq_src {
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unsigned num_types;
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atomic_t *enabled_types;
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const struct amdgpu_irq_src_funcs *funcs;
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void *data;
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};
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/* provided by interrupt generating IP blocks */
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struct amdgpu_irq_src_funcs {
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int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
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unsigned type, enum amdgpu_interrupt_state state);
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int (*process)(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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};
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struct amdgpu_irq {
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bool installed;
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spinlock_t lock;
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/* interrupt sources */
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struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID];
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/* status, etc. */
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bool msi_enabled; /* msi enabled */
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/* interrupt ring */
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struct amdgpu_ih_ring ih;
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const struct amdgpu_ih_funcs *ih_funcs;
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/* gen irq stuff */
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struct irq_domain *domain; /* GPU irq controller domain */
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unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
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};
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void amdgpu_irq_preinstall(struct drm_device *dev);
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int amdgpu_irq_postinstall(struct drm_device *dev);
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void amdgpu_irq_uninstall(struct drm_device *dev);
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irqreturn_t amdgpu_irq_handler(int irq, void *arg);
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int amdgpu_irq_init(struct amdgpu_device *adev);
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void amdgpu_irq_fini(struct amdgpu_device *adev);
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int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
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struct amdgpu_irq_src *source);
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void amdgpu_irq_dispatch(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type);
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int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type);
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bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type);
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int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type);
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bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type);
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void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
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int amdgpu_irq_add_domain(struct amdgpu_device *adev);
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void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
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unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
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#endif
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