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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a1b7cb92b4
The Keystone 2 66AK2G SoC has a single TMS320C66x DSP Core Subsystem (C66x CorePac), containing a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D SRAMs and a 1 MB L2 SRAM. Add the DT node for this DSP processor sub-system. The DT node has a new property 'power-domains' and no 'clocks' properties, and uses slightly different property values for 'resets' compared to other Keystone 2 SoCs. The processor does not have an MMU, and uses various IPC Generation registers and shared memory for inter-processor communication. The alias with a stem 'rproc' has also been added for the DSP, it provides a fixed remoteproc id for the DSP processor. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
348 lines
9.0 KiB
Plaintext
348 lines
9.0 KiB
Plaintext
/*
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* Device Tree Source for K2G SOC
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*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/keystone.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "ti,k2g","ti,keystone";
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model = "Texas Instruments K2G SoC";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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chosen { };
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aliases {
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serial0 = &uart0;
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rproc0 = &dsp0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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};
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gic: interrupt-controller@02561000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x02561000 0x0 0x1000>,
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<0x0 0x02562000 0x0 0x2000>,
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<0x0 0x02564000 0x0 0x2000>,
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<0x0 0x02566000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts =
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<GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#pinctrl-cells = <1>;
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compatible = "ti,keystone","simple-bus";
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ranges = <0x0 0x0 0x0 0xc0000000>;
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dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
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msm_ram: msmram@0c000000 {
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compatible = "mmio-sram";
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reg = <0x0c000000 0x100000>;
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ranges = <0x0 0x0c000000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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sram-bm@f7000 {
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reg = <0x000f7000 0x8000>;
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};
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};
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k2g_pinctrl: pinmux@02621000 {
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compatible = "pinctrl-single";
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reg = <0x02621000 0x410>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x001b0007>;
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};
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devctrl: device-state-control@02620000 {
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compatible = "ti,keystone-devctrl", "syscon";
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reg = <0x02620000 0x1000>;
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};
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uart0: serial@02530c00 {
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compatible = "ti,da830-uart", "ns16550a";
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current-speed = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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reg = <0x02530c00 0x100>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
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clock-frequency = <200000000>;
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status = "disabled";
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};
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dcan0: can@0260B200 {
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compatible = "ti,am4372-d_can", "ti,am3352-d_can";
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reg = <0x0260B200 0x200>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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power-domains = <&k2g_pds 0x0008>;
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clocks = <&k2g_clks 0x0008 1>;
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};
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dcan1: can@0260B400 {
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compatible = "ti,am4372-d_can", "ti,am3352-d_can";
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reg = <0x0260B400 0x200>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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power-domains = <&k2g_pds 0x0009>;
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clocks = <&k2g_clks 0x0009 1>;
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};
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kirq0: keystone_irq@026202a0 {
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compatible = "ti,keystone-irq";
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interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,syscon-dev = <&devctrl 0x2a0>;
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};
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dspgpio0: keystone_dsp_gpio@02620240 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x240>;
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};
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dsp0: dsp@10800000 {
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compatible = "ti,k2g-dsp";
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reg = <0x10800000 0x00100000>,
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<0x10e00000 0x00008000>,
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<0x10f00000 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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power-domains = <&k2g_pds 0x0046>;
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ti,syscon-dev = <&devctrl 0x844>;
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resets = <&k2g_reset 0x0046 0x1>;
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interrupt-parent = <&kirq0>;
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interrupts = <0 8>;
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interrupt-names = "vring", "exception";
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kick-gpios = <&dspgpio0 27 0>;
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status = "disabled";
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};
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msgmgr: msgmgr@02a00000 {
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compatible = "ti,k2g-message-manager";
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#mbox-cells = <2>;
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reg-names = "queue_proxy_region",
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"queue_state_debug_region";
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reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
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interrupt-names = "rx_005",
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"rx_057";
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interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmmc: pmmc@02921c00 {
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compatible = "ti,k2g-sci";
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/*
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* In case of rare platforms that does not use k2g as
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* system master, use /delete-property/
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*/
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ti,system-reboot-controller;
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mbox-names = "rx", "tx";
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mboxes= <&msgmgr 5 2>,
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<&msgmgr 0 0>;
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reg-names = "debug_messages";
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reg = <0x02921c00 0x400>;
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k2g_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <1>;
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};
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k2g_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k2g_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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gpio0: gpio@2603000 {
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compatible = "ti,k2g-gpio", "ti,keystone-gpio";
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reg = <0x02603000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <144>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&k2g_clks 0x001b 0x0>;
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clock-names = "gpio";
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};
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gpio1: gpio@260a000 {
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compatible = "ti,k2g-gpio", "ti,keystone-gpio";
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reg = <0x0260a000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <68>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&k2g_clks 0x001c 0x0>;
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clock-names = "gpio";
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};
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edma0: edma@02700000 {
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compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
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reg = <0x02700000 0x8000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "edma3_ccint", "emda3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
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ti,edma-memcpy-channels = <32 33 34 35>;
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power-domains = <&k2g_pds 0x3f>;
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};
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edma0_tptc0: tptc@02760000 {
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
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reg = <0x02760000 0x400>;
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power-domains = <&k2g_pds 0x3f>;
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};
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edma0_tptc1: tptc@02768000 {
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
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reg = <0x02768000 0x400>;
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power-domains = <&k2g_pds 0x3f>;
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};
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edma1: edma@02728000 {
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compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
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reg = <0x02728000 0x8000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "edma3_ccint", "emda3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
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/*
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* memcpy is disabled, can be enabled with:
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* ti,edma-memcpy-channels = <12 13 14 15>;
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* for example.
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*/
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power-domains = <&k2g_pds 0x4f>;
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};
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edma1_tptc0: tptc@027b0000 {
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
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reg = <0x027b0000 0x400>;
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power-domains = <&k2g_pds 0x4f>;
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};
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edma1_tptc1: tptc@027b8000 {
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
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reg = <0x027b8000 0x400>;
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power-domains = <&k2g_pds 0x4f>;
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};
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mmc0: mmc@23000000 {
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compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
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reg = <0x23000000 0x400>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
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dmas = <&edma1 24 0>, <&edma1 25 0>;
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dma-names = "tx", "rx";
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bus-width = <4>;
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ti,needs-special-reset;
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no-1-8-v;
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max-frequency = <96000000>;
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power-domains = <&k2g_pds 0xb>;
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clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
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clock-names = "fck", "mmchsdb_fck";
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status = "disabled";
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};
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mmc1: mmc@23100000 {
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compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
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reg = <0x23100000 0x400>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
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dmas = <&edma1 26 0>, <&edma1 27 0>;
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dma-names = "tx", "rx";
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bus-width = <8>;
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ti,needs-special-reset;
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ti,non-removable;
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max-frequency = <96000000>;
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power-domains = <&k2g_pds 0xc>;
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clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>;
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clock-names = "fck", "mmchsdb_fck";
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status = "disabled";
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};
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};
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};
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