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3370dc916c
atlas6 is a SoC very similar with primaII, the register layput of
pinctrl is same, but the pads, groups and functions of atlas6 have
different layout with prima2, this patch
1. pull the definition of pads, groups and functions out of the
pinctrl-sirf driver,and put them into soc-specific files
2. add pads, groups and functions tables for atlas6
3. let pads, groups and functions tables become the config data of
the related dt compatible node, so the pinctrl-sirf can support
all SiRF SoCs with the config data as private data.
In this patch,we create a sirf dir, and let
the old drivers/pinctrl/pinctrl-sirf.c =
drivers/pinctrl/sirf/pinctrl-prima2.c +
drivers/pinctrl/sirf/pinctrl-sirf.c
drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
pin layout of atlas6.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/*
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* pinmux driver shared headfile for CSR SiRFsoc
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef __PINMUX_SIRF_H__
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#define __PINMUX_SIRF_H__
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#define SIRFSOC_NUM_PADS 622
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#define SIRFSOC_RSC_PIN_MUX 0x4
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#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
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#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
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#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
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#define SIRFSOC_GPIO_DSP_EN0 (0x80)
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#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
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#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
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#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
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#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
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#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
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#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
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#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
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#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
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#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
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#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
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#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
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#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
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#define SIRFSOC_GPIO_NO_OF_BANKS 5
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#define SIRFSOC_GPIO_BANK_SIZE 32
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#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
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/**
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* @dev: a pointer back to containing device
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* @virtbase: the offset to the controller in virtual memory
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*/
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struct sirfsoc_pmx {
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struct device *dev;
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struct pinctrl_dev *pmx;
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void __iomem *gpio_virtbase;
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void __iomem *rsc_virtbase;
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u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
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u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
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u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
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u32 dspen_regs;
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u32 rsc_regs[3];
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bool is_marco;
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};
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/* SIRFSOC_GPIO_PAD_EN set */
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struct sirfsoc_muxmask {
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unsigned long group;
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unsigned long mask;
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};
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struct sirfsoc_padmux {
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unsigned long muxmask_counts;
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const struct sirfsoc_muxmask *muxmask;
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/* RSC_PIN_MUX set */
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unsigned long funcmask;
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unsigned long funcval;
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};
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/**
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* struct sirfsoc_pin_group - describes a SiRFprimaII pin group
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* @name: the name of this specific pin group
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* @pins: an array of discrete physical pins used in this group, taken
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* from the driver-local pin enumeration space
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* @num_pins: the number of pins in this group array, i.e. the number of
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* elements in .pins so we can iterate over that array
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*/
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struct sirfsoc_pin_group {
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const char *name;
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const unsigned int *pins;
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const unsigned num_pins;
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};
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#define SIRFSOC_PIN_GROUP(n, p) \
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{ \
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.name = n, \
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.pins = p, \
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.num_pins = ARRAY_SIZE(p), \
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}
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struct sirfsoc_pmx_func {
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const char *name;
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const char * const *groups;
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const unsigned num_groups;
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const struct sirfsoc_padmux *padmux;
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};
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#define SIRFSOC_PMX_FUNCTION(n, g, m) \
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{ \
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.name = n, \
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.groups = g, \
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.num_groups = ARRAY_SIZE(g), \
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.padmux = &m, \
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}
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struct sirfsoc_pinctrl_data {
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struct pinctrl_pin_desc *pads;
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int pads_cnt;
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struct sirfsoc_pin_group *grps;
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int grps_cnt;
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struct sirfsoc_pmx_func *funcs;
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int funcs_cnt;
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};
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extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
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extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
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#endif
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