mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 14:06:51 +07:00
f956a785a2
This creates a new SoC bus driver for the ARM Integrator family core modules to register the SoC bus and provide sysfs info for the core module. We delete the corresponding code from the Integrator machine and select this driver to get a clean result. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
343 lines
8.4 KiB
C
343 lines
8.4 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_ap.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/syscore_ops.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/stat.h>
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#include <linux/termios.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/setup.h>
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#include <asm/param.h> /* HZ */
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "hardware.h"
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#include "cm.h"
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#include "common.h"
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#include "pci_v3.h"
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#include "lm.h"
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/* Base address to the AP system controller */
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void __iomem *ap_syscon_base;
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/* Base address to the external bus interface */
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static void __iomem *ebi_base;
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Integrator interrupt controller (for header #0,
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* just for now).
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*/
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#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
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/*
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* Logical Physical
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* ef000000 Cache flush
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* f1100000 11000000 System controller registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* f1b00000 1b000000 GPIO
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*/
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static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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pci_v3_early_init();
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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static int irq_suspend(void)
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{
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ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
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return 0;
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}
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static void irq_resume(void)
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{
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/* disable all irq sources */
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cm_clear_irqs();
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
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}
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#else
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#define irq_suspend NULL
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#define irq_resume NULL
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#endif
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static struct syscore_ops irq_syscore_ops = {
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.suspend = irq_suspend,
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.resume = irq_resume,
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};
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static int __init irq_syscore_init(void)
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{
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register_syscore_ops(&irq_syscore_ops);
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return 0;
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}
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device_initcall(irq_syscore_init);
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/*
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* Flash handling.
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*/
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static int ap_flash_init(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
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INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
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if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
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& INTEGRATOR_EBI_WRITE_ENABLE)) {
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writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
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writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
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writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
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}
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return 0;
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}
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static void ap_flash_exit(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
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~INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
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if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
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INTEGRATOR_EBI_WRITE_ENABLE) {
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writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
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writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
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writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
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}
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}
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static void ap_flash_set_vpp(struct platform_device *pdev, int on)
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{
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if (on)
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
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ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
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else
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
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ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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}
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static struct physmap_flash_data ap_flash_data = {
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.width = 4,
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.init = ap_flash_init,
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.exit = ap_flash_exit,
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.set_vpp = ap_flash_set_vpp,
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};
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/*
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* For the PL010 found in the Integrator/AP some of the UART control is
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* implemented in the system controller and accessed using a callback
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* from the driver.
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*/
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static void integrator_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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u32 phybase = dev->res.start;
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if (phybase == INTEGRATOR_UART0_BASE) {
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/* UART0 */
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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/* UART1 */
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
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__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
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}
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struct amba_pl010_data ap_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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void __init ap_init_early(void)
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{
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}
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static void __init ap_init_irq_of(void)
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{
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cm_init();
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irqchip_init();
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}
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/* For the Device Tree, add in the UART callbacks as AUXDATA */
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static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
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"rtc", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
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"uart0", &ap_uart_data),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
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"uart1", &ap_uart_data),
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OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
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"kmi0", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
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"kmi1", NULL),
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OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
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"physmap-flash", &ap_flash_data),
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{ /* sentinel */ },
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};
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static const struct of_device_id ap_syscon_match[] = {
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{ .compatible = "arm,integrator-ap-syscon"},
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{ },
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};
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static const struct of_device_id ebi_match[] = {
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{ .compatible = "arm,external-bus-interface"},
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{ },
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};
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static void __init ap_init_of(void)
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{
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unsigned long sc_dec;
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struct device_node *syscon;
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struct device_node *ebi;
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int i;
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syscon = of_find_matching_node(NULL, ap_syscon_match);
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if (!syscon)
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return;
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ebi = of_find_matching_node(NULL, ebi_match);
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if (!ebi)
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return;
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ap_syscon_base = of_iomap(syscon, 0);
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if (!ap_syscon_base)
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return;
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ebi_base = of_iomap(ebi, 0);
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if (!ebi_base)
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return;
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of_platform_populate(NULL, of_default_bus_match_table,
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ap_auxdata_lookup, NULL);
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sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
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for (i = 0; i < 4; i++) {
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struct lm_device *lmdev;
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if ((sc_dec & (16 << i)) == 0)
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continue;
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lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
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if (!lmdev)
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continue;
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lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
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lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
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lmdev->resource.flags = IORESOURCE_MEM;
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lmdev->irq = irq_of_parse_and_map(syscon, i);
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lmdev->id = i;
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lm_device_register(lmdev);
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}
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}
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static const char * ap_dt_board_compat[] = {
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"arm,integrator-ap",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq_of,
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.init_machine = ap_init_of,
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.dt_compat = ap_dt_board_compat,
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MACHINE_END
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