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On CSR SiRFprimaII and SiRFatlasVI, the 6th timer can act as a watchdog timer when the Watchdog mode is enabled. watchdog occur when TIMER watchdog counter matches the value software pre-set, when this event occurs, the effect is the same as the system software reset. Signed-off-by: Xianglong Du <Xianglong.Du@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Cc: Romain Izard <romain.izard.pro@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
15 lines
310 B
Plaintext
15 lines
310 B
Plaintext
SiRFSoC Timer and Watchdog Timer(WDT) Controller
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Required properties:
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- compatible: "sirf,prima2-tick"
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- reg: Address range of tick timer/WDT register set
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- interrupts: interrupt number to the cpu
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Example:
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timer@b0020000 {
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compatible = "sirf,prima2-tick";
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reg = <0xb0020000 0x1000>;
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interrupts = <0>;
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};
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