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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ab394543dd
This may, perhaps, get re-merged with nvc0_graph.c at some point. It's still unclear as to how great an idea that'd be. Stay tuned... Completely dependent on firmware blobs from NVIDIA binary driver currently. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifndef __NVE0_GRAPH_H__
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#define __NVE0_GRAPH_H__
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#define GPC_MAX 4
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#define TPC_MAX 32
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#define ROP_BCAST(r) (0x408800 + (r))
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#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
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#define GPC_BCAST(r) (0x418000 + (r))
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#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
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#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
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struct nve0_graph_fuc {
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u32 *data;
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u32 size;
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};
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struct nve0_graph_priv {
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struct nouveau_exec_engine base;
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struct nve0_graph_fuc fuc409c;
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struct nve0_graph_fuc fuc409d;
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struct nve0_graph_fuc fuc41ac;
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struct nve0_graph_fuc fuc41ad;
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u8 gpc_nr;
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u8 rop_nr;
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u8 tpc_nr[GPC_MAX];
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u8 tpc_total;
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u32 grctx_size;
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u32 *grctx_vals;
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struct nouveau_gpuobj *unk4188b4;
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struct nouveau_gpuobj *unk4188b8;
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u8 magic_not_rop_nr;
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};
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struct nve0_graph_chan {
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struct nouveau_gpuobj *grctx;
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struct nouveau_gpuobj *unk408004; /* 0x418810 too */
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struct nouveau_gpuobj *unk40800c; /* 0x419004 too */
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struct nouveau_gpuobj *unk418810; /* 0x419848 too */
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struct nouveau_gpuobj *mmio;
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int mmio_nr;
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};
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int nve0_grctx_generate(struct nouveau_channel *);
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/* nve0_graph.c uses this also to determine supported chipsets */
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static inline u32
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nve0_graph_class(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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switch (dev_priv->chipset) {
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case 0xe4:
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case 0xe7:
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return 0xa097;
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default:
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return 0;
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}
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}
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#endif
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