mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 07:55:57 +07:00
1b2c2b1238
The nest mmu required an explicit flush as a tlbi would not flush it in the same way as the core. However an alternate firmware fix exists which should eliminate the need for this flush, so instead add a device-tree property (ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
868 lines
21 KiB
C
868 lines
21 KiB
C
/*
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* This file implements the DMA operations for NVLink devices. The NPU
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* devices all point to the same iommu table as the parent PCI device.
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*
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* Copyright Alistair Popple, IBM Corporation 2015.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*/
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#include <linux/slab.h>
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#include <linux/mmu_notifier.h>
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#include <linux/mmu_context.h>
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#include <linux/of.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/memblock.h>
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#include <linux/iommu.h>
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#include <asm/tlb.h>
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#include <asm/powernv.h>
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#include <asm/reg.h>
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#include <asm/opal.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/pnv-pci.h>
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#include <asm/msi_bitmap.h>
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#include <asm/opal.h>
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#include "powernv.h"
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#include "pci.h"
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#define npu_to_phb(x) container_of(x, struct pnv_phb, npu)
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/*
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* Other types of TCE cache invalidation are not functional in the
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* hardware.
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*/
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static struct pci_dev *get_pci_dev(struct device_node *dn)
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{
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return PCI_DN(dn)->pcidev;
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}
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/* Given a NPU device get the associated PCI device. */
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struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev)
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{
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struct device_node *dn;
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struct pci_dev *gpdev;
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if (WARN_ON(!npdev))
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return NULL;
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if (WARN_ON(!npdev->dev.of_node))
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return NULL;
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/* Get assoicated PCI device */
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dn = of_parse_phandle(npdev->dev.of_node, "ibm,gpu", 0);
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if (!dn)
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return NULL;
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gpdev = get_pci_dev(dn);
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of_node_put(dn);
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return gpdev;
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}
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EXPORT_SYMBOL(pnv_pci_get_gpu_dev);
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/* Given the real PCI device get a linked NPU device. */
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struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index)
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{
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struct device_node *dn;
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struct pci_dev *npdev;
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if (WARN_ON(!gpdev))
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return NULL;
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/* Not all PCI devices have device-tree nodes */
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if (!gpdev->dev.of_node)
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return NULL;
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/* Get assoicated PCI device */
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dn = of_parse_phandle(gpdev->dev.of_node, "ibm,npu", index);
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if (!dn)
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return NULL;
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npdev = get_pci_dev(dn);
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of_node_put(dn);
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return npdev;
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}
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EXPORT_SYMBOL(pnv_pci_get_npu_dev);
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#define NPU_DMA_OP_UNSUPPORTED() \
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dev_err_once(dev, "%s operation unsupported for NVLink devices\n", \
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__func__)
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static void *dma_npu_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return NULL;
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}
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static void dma_npu_free(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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}
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static dma_addr_t dma_npu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static int dma_npu_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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unsigned long attrs)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static int dma_npu_dma_supported(struct device *dev, u64 mask)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static u64 dma_npu_get_required_mask(struct device *dev)
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{
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NPU_DMA_OP_UNSUPPORTED();
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return 0;
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}
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static const struct dma_map_ops dma_npu_ops = {
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.map_page = dma_npu_map_page,
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.map_sg = dma_npu_map_sg,
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.alloc = dma_npu_alloc,
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.free = dma_npu_free,
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.dma_supported = dma_npu_dma_supported,
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.get_required_mask = dma_npu_get_required_mask,
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};
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/*
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* Returns the PE assoicated with the PCI device of the given
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* NPU. Returns the linked pci device if pci_dev != NULL.
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*/
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static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
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struct pci_dev **gpdev)
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{
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struct pnv_phb *phb;
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struct pci_controller *hose;
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struct pci_dev *pdev;
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struct pnv_ioda_pe *pe;
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struct pci_dn *pdn;
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pdev = pnv_pci_get_gpu_dev(npe->pdev);
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if (!pdev)
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return NULL;
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pdn = pci_get_pdn(pdev);
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
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return NULL;
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hose = pci_bus_to_host(pdev->bus);
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phb = hose->private_data;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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if (gpdev)
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*gpdev = pdev;
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return pe;
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}
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long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
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struct iommu_table *tbl)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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const unsigned long size = tbl->it_indirect_levels ?
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tbl->it_level_size : tbl->it_size;
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const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
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const __u64 win_size = tbl->it_size << tbl->it_page_shift;
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pe_info(npe, "Setting up window %llx..%llx pg=%lx\n",
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start_addr, start_addr + win_size - 1,
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IOMMU_PAGE_SIZE(tbl));
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rc = opal_pci_map_pe_dma_window(phb->opal_id,
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npe->pe_number,
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npe->pe_number,
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tbl->it_indirect_levels + 1,
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__pa(tbl->it_base),
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size << 3,
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IOMMU_PAGE_SIZE(tbl));
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if (rc) {
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pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
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return rc;
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}
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pnv_pci_ioda2_tce_invalidate_entire(phb, false);
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/* Add the table to the list so its TCE cache will get invalidated */
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pnv_pci_link_table_and_group(phb->hose->node, num,
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tbl, &npe->table_group);
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return 0;
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}
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long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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pe_info(npe, "Removing DMA window\n");
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rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
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npe->pe_number,
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0/* levels */, 0/* table address */,
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0/* table size */, 0/* page size */);
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if (rc) {
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pe_err(npe, "Unmapping failed, ret = %lld\n", rc);
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return rc;
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}
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pnv_pci_ioda2_tce_invalidate_entire(phb, false);
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pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
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&npe->table_group);
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return 0;
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}
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/*
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* Enables 32 bit DMA on NPU.
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*/
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static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
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{
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struct pci_dev *gpdev;
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struct pnv_ioda_pe *gpe;
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int64_t rc;
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/*
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* Find the assoicated PCI devices and get the dma window
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* information from there.
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*/
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if (!npe->pdev || !(npe->flags & PNV_IODA_PE_DEV))
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return;
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gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
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if (!gpe)
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return;
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rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
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/*
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* We don't initialise npu_pe->tce32_table as we always use
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* dma_npu_ops which are nops.
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*/
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set_dma_ops(&npe->pdev->dev, &dma_npu_ops);
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}
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/*
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* Enables bypass mode on the NPU. The NPU only supports one
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* window per link, so bypass needs to be explicitly enabled or
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* disabled. Unlike for a PHB3 bypass and non-bypass modes can't be
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* active at the same time.
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*/
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static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc = 0;
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phys_addr_t top = memblock_end_of_DRAM();
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if (phb->type != PNV_PHB_NPU || !npe->pdev)
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return -EINVAL;
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rc = pnv_npu_unset_window(npe, 0);
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if (rc != OPAL_SUCCESS)
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return rc;
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/* Enable the bypass window */
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top = roundup_pow_of_two(top);
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dev_info(&npe->pdev->dev, "Enabling bypass for PE %x\n",
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npe->pe_number);
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rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
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npe->pe_number, npe->pe_number,
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0 /* bypass base */, top);
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if (rc == OPAL_SUCCESS)
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pnv_pci_ioda2_tce_invalidate_entire(phb, false);
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return rc;
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}
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void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
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{
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int i;
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struct pnv_phb *phb;
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struct pci_dn *pdn;
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struct pnv_ioda_pe *npe;
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struct pci_dev *npdev;
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for (i = 0; ; ++i) {
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npdev = pnv_pci_get_npu_dev(gpdev, i);
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if (!npdev)
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break;
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pdn = pci_get_pdn(npdev);
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
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return;
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phb = pci_bus_to_host(npdev->bus)->private_data;
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/* We only do bypass if it's enabled on the linked device */
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npe = &phb->ioda.pe_array[pdn->pe_number];
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if (bypass) {
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dev_info(&npdev->dev,
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"Using 64-bit DMA iommu bypass\n");
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pnv_npu_dma_set_bypass(npe);
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} else {
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dev_info(&npdev->dev, "Using 32-bit DMA via iommu\n");
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pnv_npu_dma_set_32(npe);
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}
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}
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}
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/* Switch ownership from platform code to external user (e.g. VFIO) */
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void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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int64_t rc;
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/*
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* Note: NPU has just a single TVE in the hardware which means that
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* while used by the kernel, it can have either 32bit window or
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* DMA bypass but never both. So we deconfigure 32bit window only
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* if it was enabled at the moment of ownership change.
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*/
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if (npe->table_group.tables[0]) {
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pnv_npu_unset_window(npe, 0);
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return;
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}
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/* Disable bypass */
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rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
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npe->pe_number, npe->pe_number,
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0 /* bypass base */, 0);
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if (rc) {
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pe_err(npe, "Failed to disable bypass, err %lld\n", rc);
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return;
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}
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pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
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}
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struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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struct pci_bus *pbus = phb->hose->bus;
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struct pci_dev *npdev, *gpdev = NULL, *gptmp;
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struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
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if (!gpe || !gpdev)
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return NULL;
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list_for_each_entry(npdev, &pbus->devices, bus_list) {
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gptmp = pnv_pci_get_gpu_dev(npdev);
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if (gptmp != gpdev)
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continue;
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pe_info(gpe, "Attached NPU %s\n", dev_name(&npdev->dev));
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iommu_group_add_device(gpe->table_group.group, &npdev->dev);
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}
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return gpe;
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}
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/* Maximum number of nvlinks per npu */
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#define NV_MAX_LINKS 6
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/* Maximum index of npu2 hosts in the system. Always < NV_MAX_NPUS */
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static int max_npu2_index;
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struct npu_context {
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struct mm_struct *mm;
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struct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];
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struct mmu_notifier mn;
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struct kref kref;
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bool nmmu_flush;
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/* Callback to stop translation requests on a given GPU */
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struct npu_context *(*release_cb)(struct npu_context *, void *);
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/*
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* Private pointer passed to the above callback for usage by
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* device drivers.
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*/
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void *priv;
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};
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/*
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* Find a free MMIO ATSD register and mark it in use. Return -ENOSPC
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* if none are available.
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*/
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static int get_mmio_atsd_reg(struct npu *npu)
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{
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int i;
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for (i = 0; i < npu->mmio_atsd_count; i++) {
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if (!test_and_set_bit(i, &npu->mmio_atsd_usage))
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return i;
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}
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return -ENOSPC;
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}
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static void put_mmio_atsd_reg(struct npu *npu, int reg)
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{
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clear_bit(reg, &npu->mmio_atsd_usage);
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}
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/* MMIO ATSD register offsets */
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#define XTS_ATSD_AVA 1
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#define XTS_ATSD_STAT 2
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static int mmio_launch_invalidate(struct npu *npu, unsigned long launch,
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unsigned long va)
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{
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int mmio_atsd_reg;
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do {
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mmio_atsd_reg = get_mmio_atsd_reg(npu);
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cpu_relax();
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} while (mmio_atsd_reg < 0);
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__raw_writeq(cpu_to_be64(va),
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npu->mmio_atsd_regs[mmio_atsd_reg] + XTS_ATSD_AVA);
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eieio();
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__raw_writeq(cpu_to_be64(launch), npu->mmio_atsd_regs[mmio_atsd_reg]);
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return mmio_atsd_reg;
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}
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static int mmio_invalidate_pid(struct npu *npu, unsigned long pid, bool flush)
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{
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unsigned long launch;
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/* IS set to invalidate matching PID */
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launch = PPC_BIT(12);
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/* PRS set to process-scoped */
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launch |= PPC_BIT(13);
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/* AP */
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launch |= (u64) mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
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/* PID */
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launch |= pid << PPC_BITLSHIFT(38);
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/* No flush */
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launch |= !flush << PPC_BITLSHIFT(39);
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/* Invalidating the entire process doesn't use a va */
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return mmio_launch_invalidate(npu, launch, 0);
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}
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|
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static int mmio_invalidate_va(struct npu *npu, unsigned long va,
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unsigned long pid, bool flush)
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{
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unsigned long launch;
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/* IS set to invalidate target VA */
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launch = 0;
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/* PRS set to process scoped */
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launch |= PPC_BIT(13);
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/* AP */
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launch |= (u64) mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
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/* PID */
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launch |= pid << PPC_BITLSHIFT(38);
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/* No flush */
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launch |= !flush << PPC_BITLSHIFT(39);
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return mmio_launch_invalidate(npu, launch, va);
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}
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#define mn_to_npu_context(x) container_of(x, struct npu_context, mn)
|
|
|
|
struct mmio_atsd_reg {
|
|
struct npu *npu;
|
|
int reg;
|
|
};
|
|
|
|
static void mmio_invalidate_wait(
|
|
struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS], bool flush)
|
|
{
|
|
struct npu *npu;
|
|
int i, reg;
|
|
|
|
/* Wait for all invalidations to complete */
|
|
for (i = 0; i <= max_npu2_index; i++) {
|
|
if (mmio_atsd_reg[i].reg < 0)
|
|
continue;
|
|
|
|
/* Wait for completion */
|
|
npu = mmio_atsd_reg[i].npu;
|
|
reg = mmio_atsd_reg[i].reg;
|
|
while (__raw_readq(npu->mmio_atsd_regs[reg] + XTS_ATSD_STAT))
|
|
cpu_relax();
|
|
|
|
put_mmio_atsd_reg(npu, reg);
|
|
|
|
/*
|
|
* The GPU requires two flush ATSDs to ensure all entries have
|
|
* been flushed. We use PID 0 as it will never be used for a
|
|
* process on the GPU.
|
|
*/
|
|
if (flush)
|
|
mmio_invalidate_pid(npu, 0, true);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Invalidate either a single address or an entire PID depending on
|
|
* the value of va.
|
|
*/
|
|
static void mmio_invalidate(struct npu_context *npu_context, int va,
|
|
unsigned long address, bool flush)
|
|
{
|
|
int i, j;
|
|
struct npu *npu;
|
|
struct pnv_phb *nphb;
|
|
struct pci_dev *npdev;
|
|
struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
|
|
unsigned long pid = npu_context->mm->context.id;
|
|
|
|
if (npu_context->nmmu_flush)
|
|
/*
|
|
* Unfortunately the nest mmu does not support flushing specific
|
|
* addresses so we have to flush the whole mm once before
|
|
* shooting down the GPU translation.
|
|
*/
|
|
flush_all_mm(npu_context->mm);
|
|
|
|
/*
|
|
* Loop over all the NPUs this process is active on and launch
|
|
* an invalidate.
|
|
*/
|
|
for (i = 0; i <= max_npu2_index; i++) {
|
|
mmio_atsd_reg[i].reg = -1;
|
|
for (j = 0; j < NV_MAX_LINKS; j++) {
|
|
npdev = npu_context->npdev[i][j];
|
|
if (!npdev)
|
|
continue;
|
|
|
|
nphb = pci_bus_to_host(npdev->bus)->private_data;
|
|
npu = &nphb->npu;
|
|
mmio_atsd_reg[i].npu = npu;
|
|
|
|
if (va)
|
|
mmio_atsd_reg[i].reg =
|
|
mmio_invalidate_va(npu, address, pid,
|
|
flush);
|
|
else
|
|
mmio_atsd_reg[i].reg =
|
|
mmio_invalidate_pid(npu, pid, flush);
|
|
|
|
/*
|
|
* The NPU hardware forwards the shootdown to all GPUs
|
|
* so we only have to launch one shootdown per NPU.
|
|
*/
|
|
break;
|
|
}
|
|
}
|
|
|
|
mmio_invalidate_wait(mmio_atsd_reg, flush);
|
|
if (flush)
|
|
/* Wait for the flush to complete */
|
|
mmio_invalidate_wait(mmio_atsd_reg, false);
|
|
}
|
|
|
|
static void pnv_npu2_mn_release(struct mmu_notifier *mn,
|
|
struct mm_struct *mm)
|
|
{
|
|
struct npu_context *npu_context = mn_to_npu_context(mn);
|
|
|
|
/* Call into device driver to stop requests to the NMMU */
|
|
if (npu_context->release_cb)
|
|
npu_context->release_cb(npu_context, npu_context->priv);
|
|
|
|
/*
|
|
* There should be no more translation requests for this PID, but we
|
|
* need to ensure any entries for it are removed from the TLB.
|
|
*/
|
|
mmio_invalidate(npu_context, 0, 0, true);
|
|
}
|
|
|
|
static void pnv_npu2_mn_change_pte(struct mmu_notifier *mn,
|
|
struct mm_struct *mm,
|
|
unsigned long address,
|
|
pte_t pte)
|
|
{
|
|
struct npu_context *npu_context = mn_to_npu_context(mn);
|
|
|
|
mmio_invalidate(npu_context, 1, address, true);
|
|
}
|
|
|
|
static void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,
|
|
struct mm_struct *mm,
|
|
unsigned long start, unsigned long end)
|
|
{
|
|
struct npu_context *npu_context = mn_to_npu_context(mn);
|
|
unsigned long address;
|
|
|
|
for (address = start; address < end; address += PAGE_SIZE)
|
|
mmio_invalidate(npu_context, 1, address, false);
|
|
|
|
/* Do the flush only on the final addess == end */
|
|
mmio_invalidate(npu_context, 1, address, true);
|
|
}
|
|
|
|
static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
|
|
.release = pnv_npu2_mn_release,
|
|
.change_pte = pnv_npu2_mn_change_pte,
|
|
.invalidate_range = pnv_npu2_mn_invalidate_range,
|
|
};
|
|
|
|
/*
|
|
* Call into OPAL to setup the nmmu context for the current task in
|
|
* the NPU. This must be called to setup the context tables before the
|
|
* GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
|
|
*
|
|
* A release callback should be registered to allow a device driver to
|
|
* be notified that it should not launch any new translation requests
|
|
* as the final TLB invalidate is about to occur.
|
|
*
|
|
* Returns an error if there no contexts are currently available or a
|
|
* npu_context which should be passed to pnv_npu2_handle_fault().
|
|
*
|
|
* mmap_sem must be held in write mode.
|
|
*/
|
|
struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
|
|
unsigned long flags,
|
|
struct npu_context *(*cb)(struct npu_context *, void *),
|
|
void *priv)
|
|
{
|
|
int rc;
|
|
u32 nvlink_index;
|
|
struct device_node *nvlink_dn;
|
|
struct mm_struct *mm = current->mm;
|
|
struct pnv_phb *nphb;
|
|
struct npu *npu;
|
|
struct npu_context *npu_context;
|
|
|
|
/*
|
|
* At present we don't support GPUs connected to multiple NPUs and I'm
|
|
* not sure the hardware does either.
|
|
*/
|
|
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_OPAL))
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
if (!npdev)
|
|
/* No nvlink associated with this GPU device */
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
if (!mm || mm->context.id == 0) {
|
|
/*
|
|
* Kernel thread contexts are not supported and context id 0 is
|
|
* reserved on the GPU.
|
|
*/
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
nphb = pci_bus_to_host(npdev->bus)->private_data;
|
|
npu = &nphb->npu;
|
|
|
|
/*
|
|
* Setup the NPU context table for a particular GPU. These need to be
|
|
* per-GPU as we need the tables to filter ATSDs when there are no
|
|
* active contexts on a particular GPU.
|
|
*/
|
|
rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
|
|
PCI_DEVID(gpdev->bus->number, gpdev->devfn));
|
|
if (rc < 0)
|
|
return ERR_PTR(-ENOSPC);
|
|
|
|
/*
|
|
* We store the npu pci device so we can more easily get at the
|
|
* associated npus.
|
|
*/
|
|
npu_context = mm->context.npu_context;
|
|
if (!npu_context) {
|
|
npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
|
|
if (!npu_context)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
mm->context.npu_context = npu_context;
|
|
npu_context->mm = mm;
|
|
npu_context->mn.ops = &nv_nmmu_notifier_ops;
|
|
__mmu_notifier_register(&npu_context->mn, mm);
|
|
kref_init(&npu_context->kref);
|
|
} else {
|
|
kref_get(&npu_context->kref);
|
|
}
|
|
|
|
npu_context->release_cb = cb;
|
|
npu_context->priv = priv;
|
|
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
|
|
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
|
|
&nvlink_index)))
|
|
return ERR_PTR(-ENODEV);
|
|
npu_context->npdev[npu->index][nvlink_index] = npdev;
|
|
|
|
if (!nphb->npu.nmmu_flush) {
|
|
/*
|
|
* If we're not explicitly flushing ourselves we need to mark
|
|
* the thread for global flushes
|
|
*/
|
|
npu_context->nmmu_flush = false;
|
|
mm_context_add_copro(mm);
|
|
} else
|
|
npu_context->nmmu_flush = true;
|
|
|
|
return npu_context;
|
|
}
|
|
EXPORT_SYMBOL(pnv_npu2_init_context);
|
|
|
|
static void pnv_npu2_release_context(struct kref *kref)
|
|
{
|
|
struct npu_context *npu_context =
|
|
container_of(kref, struct npu_context, kref);
|
|
|
|
if (!npu_context->nmmu_flush)
|
|
mm_context_remove_copro(npu_context->mm);
|
|
|
|
npu_context->mm->context.npu_context = NULL;
|
|
mmu_notifier_unregister(&npu_context->mn,
|
|
npu_context->mm);
|
|
|
|
kfree(npu_context);
|
|
}
|
|
|
|
void pnv_npu2_destroy_context(struct npu_context *npu_context,
|
|
struct pci_dev *gpdev)
|
|
{
|
|
struct pnv_phb *nphb;
|
|
struct npu *npu;
|
|
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
|
|
struct device_node *nvlink_dn;
|
|
u32 nvlink_index;
|
|
|
|
if (WARN_ON(!npdev))
|
|
return;
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_OPAL))
|
|
return;
|
|
|
|
nphb = pci_bus_to_host(npdev->bus)->private_data;
|
|
npu = &nphb->npu;
|
|
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
|
|
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
|
|
&nvlink_index)))
|
|
return;
|
|
npu_context->npdev[npu->index][nvlink_index] = NULL;
|
|
opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id,
|
|
PCI_DEVID(gpdev->bus->number, gpdev->devfn));
|
|
kref_put(&npu_context->kref, pnv_npu2_release_context);
|
|
}
|
|
EXPORT_SYMBOL(pnv_npu2_destroy_context);
|
|
|
|
/*
|
|
* Assumes mmap_sem is held for the contexts associated mm.
|
|
*/
|
|
int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
|
|
unsigned long *flags, unsigned long *status, int count)
|
|
{
|
|
u64 rc = 0, result = 0;
|
|
int i, is_write;
|
|
struct page *page[1];
|
|
|
|
/* mmap_sem should be held so the struct_mm must be present */
|
|
struct mm_struct *mm = context->mm;
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_OPAL))
|
|
return -ENODEV;
|
|
|
|
WARN_ON(!rwsem_is_locked(&mm->mmap_sem));
|
|
|
|
for (i = 0; i < count; i++) {
|
|
is_write = flags[i] & NPU2_WRITE;
|
|
rc = get_user_pages_remote(NULL, mm, ea[i], 1,
|
|
is_write ? FOLL_WRITE : 0,
|
|
page, NULL, NULL);
|
|
|
|
/*
|
|
* To support virtualised environments we will have to do an
|
|
* access to the page to ensure it gets faulted into the
|
|
* hypervisor. For the moment virtualisation is not supported in
|
|
* other areas so leave the access out.
|
|
*/
|
|
if (rc != 1) {
|
|
status[i] = rc;
|
|
result = -EFAULT;
|
|
continue;
|
|
}
|
|
|
|
status[i] = 0;
|
|
put_page(page[0]);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
EXPORT_SYMBOL(pnv_npu2_handle_fault);
|
|
|
|
int pnv_npu2_init(struct pnv_phb *phb)
|
|
{
|
|
unsigned int i;
|
|
u64 mmio_atsd;
|
|
struct device_node *dn;
|
|
struct pci_dev *gpdev;
|
|
static int npu_index;
|
|
uint64_t rc = 0;
|
|
|
|
phb->npu.nmmu_flush =
|
|
of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
|
|
for_each_child_of_node(phb->hose->dn, dn) {
|
|
gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
|
|
if (gpdev) {
|
|
rc = opal_npu_map_lpar(phb->opal_id,
|
|
PCI_DEVID(gpdev->bus->number, gpdev->devfn),
|
|
0, 0);
|
|
if (rc)
|
|
dev_err(&gpdev->dev,
|
|
"Error %lld mapping device to LPAR\n",
|
|
rc);
|
|
}
|
|
}
|
|
|
|
for (i = 0; !of_property_read_u64_index(phb->hose->dn, "ibm,mmio-atsd",
|
|
i, &mmio_atsd); i++)
|
|
phb->npu.mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
|
|
|
|
pr_info("NPU%lld: Found %d MMIO ATSD registers", phb->opal_id, i);
|
|
phb->npu.mmio_atsd_count = i;
|
|
phb->npu.mmio_atsd_usage = 0;
|
|
npu_index++;
|
|
if (WARN_ON(npu_index >= NV_MAX_NPUS))
|
|
return -ENOSPC;
|
|
max_npu2_index = npu_index;
|
|
phb->npu.index = npu_index;
|
|
|
|
return 0;
|
|
}
|