mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 11:44:22 +07:00
4971f090aa
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJcExwOAAoJEAx081l5xIa+euIP/1NZZvSB+bsCtOwDG8I6uWsS OU5JUZ8q2dqyyFagRxzlkeSt3uWJqKp5NyNwuc9z/5u6AGF+3/97D0J1lG6Os/st 4abF6NadivYJ4cXhJ1ddIHOFMVDcAsyMWNDb93NwPwncCsQ0jt5FFOsrCyj6BGY+ ihHFlHrIyDrbBGDHz+u1E/EO5WkNnaLDoC+/k2fTRWCNI3bQL3O+orsYTI6S2uvU lQJnRfYAllgLD2p1k/rrBHcHXBv50roR0e8uhGmbdhGdp5bEW30UGBLHXxQjjSVy fQCwFwTO8X6zoxU53Zbbk+MVrp+jkTHcGKViHRuLkaHzE5mX26UXDwlXdN32ZUbK yHOJp+uDaWXX7MIz0LsB9Iqj2+eIUoFaIJMoZTMGVTNvqnTxKnoHnjAtbTH2u258 teFgmy4BIgPgo2kwEnBEZjCapou0Eivyut2wq8bTAB2Fe8LwURJpr3cioTtMLlUO L5/PoD27eFvBCAeFrQIwF3b2XiQEnBpXocmilEwP1xDMPgoyeePAfIF2iEpDvi0U jce3rLd2yVvo92xYUgoHkVTD8si/pKKnZ1D0U3+RI6pxK6s0HJEHjcNEMdvdm+2S 4qgvBQV3wlWFkXEK8PR5BHPoLntg18tKon/BTLBjgGkN9E1o9fWs1/s6KQGY4xdo l3Vvfx2LTdkgEoBssSwB =wh4W -----END PGP SIGNATURE----- Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Core: - shared fencing staging removal - drop transactional atomic helpers and move helpers to new location - DP/MST atomic cleanup - Leasing cleanups and drop EXPORT_SYMBOL - Convert drivers to atomic helpers and generic fbdev. - removed deprecated obj_ref/unref in favour of get/put - Improve dumb callback documentation - MODESET_LOCK_BEGIN/END helpers panels: - CDTech panels, Banana Pi Panel, DLC1010GIG, - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA, - Himax HX8357D, simulated RTSM AEMv8. - GPD Win2 panel - AUO G101EVN010 vgem: - render node support ttm: - move global init out of drivers - fix LRU handling for ghost objects - Support for simultaneous submissions to multiple engines scheduler: - timeout/fault handling changes to help GPU recovery - helpers for hw with preemption support i915: - Scaler/Watermark fixes - DP MST + powerwell fixes - PSR fixes - Break long get/put shmemfs pages - Icelake fixes - Icelake DSI video mode enablement - Engine workaround improvements amdgpu: - freesync support - GPU reset enabled on CI, VI, SOC15 dGPUs - ABM support in DC - KFD support for vega12/polaris12 - SDMA paging queue on vega - More amdkfd code sharing - DCC scanout on GFX9 - DC kerneldoc - Updated SMU firmware for GFX8 chips - XGMI PSP + hive reset support - GPU reset - DC trace support - Powerplay updates for newer Polaris - Cursor plane update fast path - kfd dma-buf support virtio-gpu: - add EDID support vmwgfx: - pageflip with damage support nouveau: - Initial Turing TU104/TU106 modesetting support msm: - a2xx gpu support for apq8060 and imx5 - a2xx gpummu support - mdp4 display support for apq8060 - DPU fixes and cleanups - enhanced profiling support - debug object naming interface - get_iova/page pinning decoupling tegra: - Tegra194 host1x, VIC and display support enabled - Audio over HDMI for Tegra186 and Tegra194 exynos: - DMA/IOMMU refactoring - plane alpha + blend mode support - Color format fixes for mixer driver rcar-du: - R8A7744 and R8A77470 support - R8A77965 LVDS support imx: - fbdev emulation fix - multi-tiled scalling fixes - SPDX identifiers rockchip - dw_hdmi support - dw-mipi-dsi + dual dsi support - mailbox read size fix qxl: - fix cursor pinning vc4: - YUV support (scaling + cursor) v3d: - enable TFU (Texture Formatting Unit) mali-dp: - add support for linear tiled formats sun4i: - Display Engine 3 support - H6 DE3 mixer 0 support - H6 display engine support - dw-hdmi support - H6 HDMI phy support - implicit fence waiting - BGRX8888 support meson: - Overlay plane support - implicit fence waiting - HDMI 1.4 4k modes bridge: - i2c fixes for sii902x" * tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits) drm/amd/display: Add fast path for cursor plane updates drm/amdgpu: Enable GPU recovery by default for CI drm/amd/display: Fix duplicating scaling/underscan connector state drm/amd/display: Fix unintialized max_bpc state values Revert "drm/amd/display: Set RMX_ASPECT as default" drm/amdgpu: Fix stub function name drm/msm/dpu: Fix clock issue after bind failure drm/msm/dpu: Clean up dpu_media_info.h static inline functions drm/msm/dpu: Further cleanups for static inline functions drm/msm/dpu: Cleanup the debugfs functions drm/msm/dpu: Remove dpu_irq and unused functions drm/msm: Make irq_postinstall optional drm/msm/dpu: Cleanup callers of dpu_hw_blk_init drm/msm/dpu: Remove unused functions drm/msm/dpu: Remove dpu_crtc_is_enabled() drm/msm/dpu: Remove dpu_crtc_get_mixer_height drm/msm/dpu: Remove dpu_dbg drm/msm: dpu: Remove crtc_lock drm/msm: dpu: Remove vblank_requested flag from dpu_crtc drm/msm: dpu: Separate crtc assignment from vblank enable ...
1023 lines
24 KiB
C
1023 lines
24 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_gpu.h"
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#include "msm_gem.h"
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#include "msm_mmu.h"
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#include "msm_fence.h"
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#include "msm_gpu_trace.h"
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#include "adreno/adreno_gpu.h"
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#include <generated/utsrelease.h>
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#include <linux/string_helpers.h>
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#include <linux/pm_opp.h>
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#include <linux/devfreq.h>
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#include <linux/devcoredump.h>
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/*
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* Power Management:
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*/
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static int msm_devfreq_target(struct device *dev, unsigned long *freq,
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u32 flags)
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{
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struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
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struct dev_pm_opp *opp;
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opp = devfreq_recommended_opp(dev, freq, flags);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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if (gpu->funcs->gpu_set_freq)
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gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
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else
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clk_set_rate(gpu->core_clk, *freq);
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dev_pm_opp_put(opp);
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return 0;
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}
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static int msm_devfreq_get_dev_status(struct device *dev,
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struct devfreq_dev_status *status)
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{
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struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
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ktime_t time;
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if (gpu->funcs->gpu_get_freq)
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status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
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else
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status->current_frequency = clk_get_rate(gpu->core_clk);
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status->busy_time = gpu->funcs->gpu_busy(gpu);
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time = ktime_get();
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status->total_time = ktime_us_delta(time, gpu->devfreq.time);
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gpu->devfreq.time = time;
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return 0;
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}
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static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
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{
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struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
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if (gpu->funcs->gpu_get_freq)
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*freq = gpu->funcs->gpu_get_freq(gpu);
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else
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*freq = clk_get_rate(gpu->core_clk);
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return 0;
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}
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static struct devfreq_dev_profile msm_devfreq_profile = {
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.polling_ms = 10,
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.target = msm_devfreq_target,
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.get_dev_status = msm_devfreq_get_dev_status,
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.get_cur_freq = msm_devfreq_get_cur_freq,
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};
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static void msm_devfreq_init(struct msm_gpu *gpu)
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{
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/* We need target support to do devfreq */
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if (!gpu->funcs->gpu_busy)
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return;
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msm_devfreq_profile.initial_freq = gpu->fast_rate;
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/*
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* Don't set the freq_table or max_state and let devfreq build the table
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* from OPP
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*/
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gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
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&msm_devfreq_profile, "simple_ondemand", NULL);
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if (IS_ERR(gpu->devfreq.devfreq)) {
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DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
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gpu->devfreq.devfreq = NULL;
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}
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devfreq_suspend_device(gpu->devfreq.devfreq);
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}
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static int enable_pwrrail(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret = 0;
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if (gpu->gpu_reg) {
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ret = regulator_enable(gpu->gpu_reg);
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if (ret) {
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DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
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return ret;
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}
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}
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if (gpu->gpu_cx) {
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ret = regulator_enable(gpu->gpu_cx);
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if (ret) {
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DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int disable_pwrrail(struct msm_gpu *gpu)
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{
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if (gpu->gpu_cx)
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regulator_disable(gpu->gpu_cx);
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if (gpu->gpu_reg)
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regulator_disable(gpu->gpu_reg);
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return 0;
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}
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static int enable_clk(struct msm_gpu *gpu)
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{
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if (gpu->core_clk && gpu->fast_rate)
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clk_set_rate(gpu->core_clk, gpu->fast_rate);
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/* Set the RBBM timer rate to 19.2Mhz */
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if (gpu->rbbmtimer_clk)
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clk_set_rate(gpu->rbbmtimer_clk, 19200000);
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return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
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}
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static int disable_clk(struct msm_gpu *gpu)
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{
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clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
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/*
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* Set the clock to a deliberately low rate. On older targets the clock
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* speed had to be non zero to avoid problems. On newer targets this
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* will be rounded down to zero anyway so it all works out.
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*/
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if (gpu->core_clk)
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clk_set_rate(gpu->core_clk, 27000000);
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if (gpu->rbbmtimer_clk)
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clk_set_rate(gpu->rbbmtimer_clk, 0);
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return 0;
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}
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static int enable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_prepare_enable(gpu->ebi1_clk);
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return 0;
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}
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static int disable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_disable_unprepare(gpu->ebi1_clk);
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return 0;
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}
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void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
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{
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gpu->devfreq.busy_cycles = 0;
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gpu->devfreq.time = ktime_get();
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devfreq_resume_device(gpu->devfreq.devfreq);
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}
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int msm_gpu_pm_resume(struct msm_gpu *gpu)
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{
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int ret;
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DBG("%s", gpu->name);
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ret = enable_pwrrail(gpu);
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if (ret)
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return ret;
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ret = enable_clk(gpu);
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if (ret)
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return ret;
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ret = enable_axi(gpu);
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if (ret)
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return ret;
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msm_gpu_resume_devfreq(gpu);
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gpu->needs_hw_init = true;
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return 0;
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu)
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{
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int ret;
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DBG("%s", gpu->name);
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devfreq_suspend_device(gpu->devfreq.devfreq);
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ret = disable_axi(gpu);
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if (ret)
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return ret;
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ret = disable_clk(gpu);
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if (ret)
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return ret;
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ret = disable_pwrrail(gpu);
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if (ret)
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return ret;
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return 0;
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}
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int msm_gpu_hw_init(struct msm_gpu *gpu)
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{
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int ret;
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WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
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if (!gpu->needs_hw_init)
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return 0;
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disable_irq(gpu->irq);
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ret = gpu->funcs->hw_init(gpu);
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if (!ret)
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gpu->needs_hw_init = false;
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enable_irq(gpu->irq);
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return ret;
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}
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#ifdef CONFIG_DEV_COREDUMP
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static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
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size_t count, void *data, size_t datalen)
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{
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struct msm_gpu *gpu = data;
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struct drm_print_iterator iter;
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struct drm_printer p;
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struct msm_gpu_state *state;
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state = msm_gpu_crashstate_get(gpu);
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if (!state)
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return 0;
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iter.data = buffer;
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iter.offset = 0;
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iter.start = offset;
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iter.remain = count;
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p = drm_coredump_printer(&iter);
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drm_printf(&p, "---\n");
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drm_printf(&p, "kernel: " UTS_RELEASE "\n");
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drm_printf(&p, "module: " KBUILD_MODNAME "\n");
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drm_printf(&p, "time: %lld.%09ld\n",
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state->time.tv_sec, state->time.tv_nsec);
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if (state->comm)
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drm_printf(&p, "comm: %s\n", state->comm);
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if (state->cmd)
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drm_printf(&p, "cmdline: %s\n", state->cmd);
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gpu->funcs->show(gpu, state, &p);
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msm_gpu_crashstate_put(gpu);
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return count - iter.remain;
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}
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static void msm_gpu_devcoredump_free(void *data)
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{
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struct msm_gpu *gpu = data;
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msm_gpu_crashstate_put(gpu);
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}
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static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
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struct msm_gem_object *obj, u64 iova, u32 flags)
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{
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struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
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/* Don't record write only objects */
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state_bo->size = obj->base.size;
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state_bo->iova = iova;
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/* Only store data for non imported buffer objects marked for read */
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if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
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void *ptr;
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state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
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if (!state_bo->data)
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goto out;
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ptr = msm_gem_get_vaddr_active(&obj->base);
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if (IS_ERR(ptr)) {
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kvfree(state_bo->data);
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state_bo->data = NULL;
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goto out;
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}
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memcpy(state_bo->data, ptr, obj->base.size);
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msm_gem_put_vaddr(&obj->base);
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}
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out:
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state->nr_bos++;
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}
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static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
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struct msm_gem_submit *submit, char *comm, char *cmd)
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{
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struct msm_gpu_state *state;
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/* Check if the target supports capturing crash state */
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if (!gpu->funcs->gpu_state_get)
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return;
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/* Only save one crash state at a time */
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if (gpu->crashstate)
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return;
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state = gpu->funcs->gpu_state_get(gpu);
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if (IS_ERR_OR_NULL(state))
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return;
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/* Fill in the additional crash state information */
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state->comm = kstrdup(comm, GFP_KERNEL);
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state->cmd = kstrdup(cmd, GFP_KERNEL);
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if (submit) {
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int i;
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state->bos = kcalloc(submit->nr_cmds,
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sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
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for (i = 0; state->bos && i < submit->nr_cmds; i++) {
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int idx = submit->cmd[i].idx;
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msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
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submit->bos[idx].iova, submit->bos[idx].flags);
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}
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}
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/* Set the active crash state to be dumped on failure */
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gpu->crashstate = state;
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/* FIXME: Release the crashstate if this errors out? */
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dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
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msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
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}
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#else
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static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
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struct msm_gem_submit *submit, char *comm, char *cmd)
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{
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}
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#endif
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/*
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* Hangcheck detection for locked gpu:
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*/
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static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
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uint32_t fence)
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{
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struct msm_gem_submit *submit;
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list_for_each_entry(submit, &ring->submits, node) {
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if (submit->seqno > fence)
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break;
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msm_update_fence(submit->ring->fctx,
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submit->fence->seqno);
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}
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}
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static struct msm_gem_submit *
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find_submit(struct msm_ringbuffer *ring, uint32_t fence)
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{
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struct msm_gem_submit *submit;
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WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
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list_for_each_entry(submit, &ring->submits, node)
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if (submit->seqno == fence)
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return submit;
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return NULL;
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}
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static void retire_submits(struct msm_gpu *gpu);
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static void recover_worker(struct work_struct *work)
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{
|
|
struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
|
|
struct drm_device *dev = gpu->dev;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_gem_submit *submit;
|
|
struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
|
|
char *comm = NULL, *cmd = NULL;
|
|
int i;
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
|
|
|
|
submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
|
|
if (submit) {
|
|
struct task_struct *task;
|
|
|
|
task = get_pid_task(submit->pid, PIDTYPE_PID);
|
|
if (task) {
|
|
comm = kstrdup(task->comm, GFP_KERNEL);
|
|
|
|
/*
|
|
* So slightly annoying, in other paths like
|
|
* mmap'ing gem buffers, mmap_sem is acquired
|
|
* before struct_mutex, which means we can't
|
|
* hold struct_mutex across the call to
|
|
* get_cmdline(). But submits are retired
|
|
* from the same in-order workqueue, so we can
|
|
* safely drop the lock here without worrying
|
|
* about the submit going away.
|
|
*/
|
|
mutex_unlock(&dev->struct_mutex);
|
|
cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
|
|
put_task_struct(task);
|
|
mutex_lock(&dev->struct_mutex);
|
|
}
|
|
|
|
if (comm && cmd) {
|
|
DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
|
|
gpu->name, comm, cmd);
|
|
|
|
msm_rd_dump_submit(priv->hangrd, submit,
|
|
"offending task: %s (%s)", comm, cmd);
|
|
} else
|
|
msm_rd_dump_submit(priv->hangrd, submit, NULL);
|
|
}
|
|
|
|
/* Record the crash state */
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
|
|
pm_runtime_put_sync(&gpu->pdev->dev);
|
|
|
|
kfree(cmd);
|
|
kfree(comm);
|
|
|
|
/*
|
|
* Update all the rings with the latest and greatest fence.. this
|
|
* needs to happen after msm_rd_dump_submit() to ensure that the
|
|
* bo's referenced by the offending submit are still around.
|
|
*/
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct msm_ringbuffer *ring = gpu->rb[i];
|
|
|
|
uint32_t fence = ring->memptrs->fence;
|
|
|
|
/*
|
|
* For the current (faulting?) ring/submit advance the fence by
|
|
* one more to clear the faulting submit
|
|
*/
|
|
if (ring == cur_ring)
|
|
fence++;
|
|
|
|
update_fences(gpu, ring, fence);
|
|
}
|
|
|
|
if (msm_gpu_active(gpu)) {
|
|
/* retire completed submits, plus the one that hung: */
|
|
retire_submits(gpu);
|
|
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
gpu->funcs->recover(gpu);
|
|
pm_runtime_put_sync(&gpu->pdev->dev);
|
|
|
|
/*
|
|
* Replay all remaining submits starting with highest priority
|
|
* ring
|
|
*/
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct msm_ringbuffer *ring = gpu->rb[i];
|
|
|
|
list_for_each_entry(submit, &ring->submits, node)
|
|
gpu->funcs->submit(gpu, submit, NULL);
|
|
}
|
|
}
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
msm_gpu_retire(gpu);
|
|
}
|
|
|
|
static void hangcheck_timer_reset(struct msm_gpu *gpu)
|
|
{
|
|
DBG("%s", gpu->name);
|
|
mod_timer(&gpu->hangcheck_timer,
|
|
round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
|
|
}
|
|
|
|
static void hangcheck_handler(struct timer_list *t)
|
|
{
|
|
struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
|
|
struct drm_device *dev = gpu->dev;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
|
|
uint32_t fence = ring->memptrs->fence;
|
|
|
|
if (fence != ring->hangcheck_fence) {
|
|
/* some progress has been made.. ya! */
|
|
ring->hangcheck_fence = fence;
|
|
} else if (fence < ring->seqno) {
|
|
/* no progress and not done.. hung! */
|
|
ring->hangcheck_fence = fence;
|
|
DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
|
|
gpu->name, ring->id);
|
|
DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
|
|
gpu->name, fence);
|
|
DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
|
|
gpu->name, ring->seqno);
|
|
|
|
queue_work(priv->wq, &gpu->recover_work);
|
|
}
|
|
|
|
/* if still more pending work, reset the hangcheck timer: */
|
|
if (ring->seqno > ring->hangcheck_fence)
|
|
hangcheck_timer_reset(gpu);
|
|
|
|
/* workaround for missing irq: */
|
|
queue_work(priv->wq, &gpu->retire_work);
|
|
}
|
|
|
|
/*
|
|
* Performance Counters:
|
|
*/
|
|
|
|
/* called under perf_lock */
|
|
static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
|
|
{
|
|
uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
|
|
int i, n = min(ncntrs, gpu->num_perfcntrs);
|
|
|
|
/* read current values: */
|
|
for (i = 0; i < gpu->num_perfcntrs; i++)
|
|
current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
|
|
|
|
/* update cntrs: */
|
|
for (i = 0; i < n; i++)
|
|
cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
|
|
|
|
/* save current values: */
|
|
for (i = 0; i < gpu->num_perfcntrs; i++)
|
|
gpu->last_cntrs[i] = current_cntrs[i];
|
|
|
|
return n;
|
|
}
|
|
|
|
static void update_sw_cntrs(struct msm_gpu *gpu)
|
|
{
|
|
ktime_t time;
|
|
uint32_t elapsed;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
if (!gpu->perfcntr_active)
|
|
goto out;
|
|
|
|
time = ktime_get();
|
|
elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
|
|
|
|
gpu->totaltime += elapsed;
|
|
if (gpu->last_sample.active)
|
|
gpu->activetime += elapsed;
|
|
|
|
gpu->last_sample.active = msm_gpu_active(gpu);
|
|
gpu->last_sample.time = time;
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
}
|
|
|
|
void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
|
|
{
|
|
unsigned long flags;
|
|
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
/* we could dynamically enable/disable perfcntr registers too.. */
|
|
gpu->last_sample.active = msm_gpu_active(gpu);
|
|
gpu->last_sample.time = ktime_get();
|
|
gpu->activetime = gpu->totaltime = 0;
|
|
gpu->perfcntr_active = true;
|
|
update_hw_cntrs(gpu, 0, NULL);
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
}
|
|
|
|
void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
|
|
{
|
|
gpu->perfcntr_active = false;
|
|
pm_runtime_put_sync(&gpu->pdev->dev);
|
|
}
|
|
|
|
/* returns -errno or # of cntrs sampled */
|
|
int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
|
|
uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
|
|
{
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&gpu->perf_lock, flags);
|
|
|
|
if (!gpu->perfcntr_active) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
*activetime = gpu->activetime;
|
|
*totaltime = gpu->totaltime;
|
|
|
|
gpu->activetime = gpu->totaltime = 0;
|
|
|
|
ret = update_hw_cntrs(gpu, ncntrs, cntrs);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&gpu->perf_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Cmdstream submission/retirement:
|
|
*/
|
|
|
|
static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
|
|
struct msm_gem_submit *submit)
|
|
{
|
|
int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
|
|
volatile struct msm_gpu_submit_stats *stats;
|
|
u64 elapsed, clock = 0;
|
|
int i;
|
|
|
|
stats = &ring->memptrs->stats[index];
|
|
/* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
|
|
elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
|
|
do_div(elapsed, 192);
|
|
|
|
/* Calculate the clock frequency from the number of CP cycles */
|
|
if (elapsed) {
|
|
clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
|
|
do_div(clock, elapsed);
|
|
}
|
|
|
|
trace_msm_gpu_submit_retired(submit, elapsed, clock,
|
|
stats->alwayson_start, stats->alwayson_end);
|
|
|
|
for (i = 0; i < submit->nr_bos; i++) {
|
|
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
|
/* move to inactive: */
|
|
msm_gem_move_to_inactive(&msm_obj->base);
|
|
msm_gem_unpin_iova(&msm_obj->base, gpu->aspace);
|
|
drm_gem_object_put(&msm_obj->base);
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(&gpu->pdev->dev);
|
|
pm_runtime_put_autosuspend(&gpu->pdev->dev);
|
|
msm_gem_submit_free(submit);
|
|
}
|
|
|
|
static void retire_submits(struct msm_gpu *gpu)
|
|
{
|
|
struct drm_device *dev = gpu->dev;
|
|
struct msm_gem_submit *submit, *tmp;
|
|
int i;
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
|
|
|
/* Retire the commits starting with highest priority */
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct msm_ringbuffer *ring = gpu->rb[i];
|
|
|
|
list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
|
|
if (dma_fence_is_signaled(submit->fence))
|
|
retire_submit(gpu, ring, submit);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void retire_worker(struct work_struct *work)
|
|
{
|
|
struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
|
|
struct drm_device *dev = gpu->dev;
|
|
int i;
|
|
|
|
for (i = 0; i < gpu->nr_rings; i++)
|
|
update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
retire_submits(gpu);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
}
|
|
|
|
/* call from irq handler to schedule work to retire bo's */
|
|
void msm_gpu_retire(struct msm_gpu *gpu)
|
|
{
|
|
struct msm_drm_private *priv = gpu->dev->dev_private;
|
|
queue_work(priv->wq, &gpu->retire_work);
|
|
update_sw_cntrs(gpu);
|
|
}
|
|
|
|
/* add bo's to gpu's ring, and kick gpu: */
|
|
void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
|
struct msm_file_private *ctx)
|
|
{
|
|
struct drm_device *dev = gpu->dev;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_ringbuffer *ring = submit->ring;
|
|
int i;
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
|
|
|
pm_runtime_get_sync(&gpu->pdev->dev);
|
|
|
|
msm_gpu_hw_init(gpu);
|
|
|
|
submit->seqno = ++ring->seqno;
|
|
|
|
list_add_tail(&submit->node, &ring->submits);
|
|
|
|
msm_rd_dump_submit(priv->rd, submit, NULL);
|
|
|
|
update_sw_cntrs(gpu);
|
|
|
|
for (i = 0; i < submit->nr_bos; i++) {
|
|
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
|
uint64_t iova;
|
|
|
|
/* can't happen yet.. but when we add 2d support we'll have
|
|
* to deal w/ cross-ring synchronization:
|
|
*/
|
|
WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
|
|
|
|
/* submit takes a reference to the bo and iova until retired: */
|
|
drm_gem_object_get(&msm_obj->base);
|
|
msm_gem_get_and_pin_iova(&msm_obj->base,
|
|
submit->gpu->aspace, &iova);
|
|
|
|
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
|
|
else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
|
|
}
|
|
|
|
gpu->funcs->submit(gpu, submit, ctx);
|
|
priv->lastctx = ctx;
|
|
|
|
hangcheck_timer_reset(gpu);
|
|
}
|
|
|
|
/*
|
|
* Init/Cleanup:
|
|
*/
|
|
|
|
static irqreturn_t irq_handler(int irq, void *data)
|
|
{
|
|
struct msm_gpu *gpu = data;
|
|
return gpu->funcs->irq(gpu);
|
|
}
|
|
|
|
static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
|
|
{
|
|
int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks);
|
|
|
|
if (ret < 1) {
|
|
gpu->nr_clocks = 0;
|
|
return ret;
|
|
}
|
|
|
|
gpu->nr_clocks = ret;
|
|
|
|
gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
|
|
gpu->nr_clocks, "core");
|
|
|
|
gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
|
|
gpu->nr_clocks, "rbbmtimer");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct msm_gem_address_space *
|
|
msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
|
|
uint64_t va_start, uint64_t va_end)
|
|
{
|
|
struct msm_gem_address_space *aspace;
|
|
int ret;
|
|
|
|
/*
|
|
* Setup IOMMU.. eventually we will (I think) do this once per context
|
|
* and have separate page tables per context. For now, to keep things
|
|
* simple and to get something working, just use a single address space:
|
|
*/
|
|
if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
|
|
struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
|
|
if (!iommu)
|
|
return NULL;
|
|
|
|
iommu->geometry.aperture_start = va_start;
|
|
iommu->geometry.aperture_end = va_end;
|
|
|
|
DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
|
|
|
|
aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
|
|
if (IS_ERR(aspace))
|
|
iommu_domain_free(iommu);
|
|
} else {
|
|
aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
|
|
va_start, va_end);
|
|
}
|
|
|
|
if (IS_ERR(aspace)) {
|
|
DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
|
|
PTR_ERR(aspace));
|
|
return ERR_CAST(aspace);
|
|
}
|
|
|
|
ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
|
|
if (ret) {
|
|
msm_gem_address_space_put(aspace);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return aspace;
|
|
}
|
|
|
|
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
|
|
const char *name, struct msm_gpu_config *config)
|
|
{
|
|
int i, ret, nr_rings = config->nr_rings;
|
|
void *memptrs;
|
|
uint64_t memptrs_iova;
|
|
|
|
if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
|
|
gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
|
|
|
|
gpu->dev = drm;
|
|
gpu->funcs = funcs;
|
|
gpu->name = name;
|
|
|
|
INIT_LIST_HEAD(&gpu->active_list);
|
|
INIT_WORK(&gpu->retire_work, retire_worker);
|
|
INIT_WORK(&gpu->recover_work, recover_worker);
|
|
|
|
|
|
timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
|
|
|
|
spin_lock_init(&gpu->perf_lock);
|
|
|
|
|
|
/* Map registers: */
|
|
gpu->mmio = msm_ioremap(pdev, config->ioname, name);
|
|
if (IS_ERR(gpu->mmio)) {
|
|
ret = PTR_ERR(gpu->mmio);
|
|
goto fail;
|
|
}
|
|
|
|
/* Get Interrupt: */
|
|
gpu->irq = platform_get_irq_byname(pdev, config->irqname);
|
|
if (gpu->irq < 0) {
|
|
ret = gpu->irq;
|
|
DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
|
|
goto fail;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
|
|
IRQF_TRIGGER_HIGH, gpu->name, gpu);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
|
|
goto fail;
|
|
}
|
|
|
|
ret = get_clocks(pdev, gpu);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
gpu->ebi1_clk = msm_clk_get(pdev, "bus");
|
|
DBG("ebi1_clk: %p", gpu->ebi1_clk);
|
|
if (IS_ERR(gpu->ebi1_clk))
|
|
gpu->ebi1_clk = NULL;
|
|
|
|
/* Acquire regulators: */
|
|
gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
|
|
DBG("gpu_reg: %p", gpu->gpu_reg);
|
|
if (IS_ERR(gpu->gpu_reg))
|
|
gpu->gpu_reg = NULL;
|
|
|
|
gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
|
|
DBG("gpu_cx: %p", gpu->gpu_cx);
|
|
if (IS_ERR(gpu->gpu_cx))
|
|
gpu->gpu_cx = NULL;
|
|
|
|
gpu->pdev = pdev;
|
|
platform_set_drvdata(pdev, gpu);
|
|
|
|
msm_devfreq_init(gpu);
|
|
|
|
gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
|
|
config->va_start, config->va_end);
|
|
|
|
if (gpu->aspace == NULL)
|
|
DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
|
|
else if (IS_ERR(gpu->aspace)) {
|
|
ret = PTR_ERR(gpu->aspace);
|
|
goto fail;
|
|
}
|
|
|
|
memptrs = msm_gem_kernel_new(drm,
|
|
sizeof(struct msm_rbmemptrs) * nr_rings,
|
|
MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
|
|
&memptrs_iova);
|
|
|
|
if (IS_ERR(memptrs)) {
|
|
ret = PTR_ERR(memptrs);
|
|
DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
|
|
goto fail;
|
|
}
|
|
|
|
msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
|
|
|
|
if (nr_rings > ARRAY_SIZE(gpu->rb)) {
|
|
DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
|
|
ARRAY_SIZE(gpu->rb));
|
|
nr_rings = ARRAY_SIZE(gpu->rb);
|
|
}
|
|
|
|
/* Create ringbuffer(s): */
|
|
for (i = 0; i < nr_rings; i++) {
|
|
gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
|
|
|
|
if (IS_ERR(gpu->rb[i])) {
|
|
ret = PTR_ERR(gpu->rb[i]);
|
|
DRM_DEV_ERROR(drm->dev,
|
|
"could not create ringbuffer %d: %d\n", i, ret);
|
|
goto fail;
|
|
}
|
|
|
|
memptrs += sizeof(struct msm_rbmemptrs);
|
|
memptrs_iova += sizeof(struct msm_rbmemptrs);
|
|
}
|
|
|
|
gpu->nr_rings = nr_rings;
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
|
|
msm_ringbuffer_destroy(gpu->rb[i]);
|
|
gpu->rb[i] = NULL;
|
|
}
|
|
|
|
msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
return ret;
|
|
}
|
|
|
|
void msm_gpu_cleanup(struct msm_gpu *gpu)
|
|
{
|
|
int i;
|
|
|
|
DBG("%s", gpu->name);
|
|
|
|
WARN_ON(!list_empty(&gpu->active_list));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
|
|
msm_ringbuffer_destroy(gpu->rb[i]);
|
|
gpu->rb[i] = NULL;
|
|
}
|
|
|
|
msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
|
|
|
|
if (!IS_ERR_OR_NULL(gpu->aspace)) {
|
|
gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
|
|
NULL, 0);
|
|
msm_gem_address_space_put(gpu->aspace);
|
|
}
|
|
}
|