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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ee44563596
SoCs that contain MDP5 have a top level wrapper called MDSS that manages locks, power and irq for the sub-blocks within it. Irq for HDMI is also routed through the MDSS. Shortly after the Hot Plug Detection (HPD) is enabled in HDMI, HDMI interrupts are recieved by the MDSS interrupt handler. However at this moment the HDMI irq is still not mapped to the MDSS irq domain so the HDMI irq handler cannot be called to process the interrupts. This leads to a flood of HDMI interrupts on CPU 0. If we are lucky to have the HDMI initialization running on a different CPU, it will eventually map the HDMI irq to MDSS irq domain, the next HDMI interrupt will be handled by the HDMI irq handler, the interrupt flood will stop and we will recover. If the HDMI initialization is running on CPU 0, then it cannot complete and there is nothing to stop the interrupt flood on CPU 0. The system is stuck. Fix this by moving the HPD enablement after the HDMI irq is mapped to the MDSS irq domain. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
279 lines
6.8 KiB
C
279 lines
6.8 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HDMI_CONNECTOR_H__
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#define __HDMI_CONNECTOR_H__
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/hdmi.h>
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#include "msm_drv.h"
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#include "hdmi.xml.h"
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#define HDMI_MAX_NUM_GPIO 6
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struct hdmi_phy;
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struct hdmi_platform_config;
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struct hdmi_gpio_data {
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int num;
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bool output;
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int value;
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const char *label;
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};
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struct hdmi_audio {
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bool enabled;
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struct hdmi_audio_infoframe infoframe;
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int rate;
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};
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struct hdmi_hdcp_ctrl;
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struct hdmi {
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struct drm_device *dev;
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struct platform_device *pdev;
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struct platform_device *audio_pdev;
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const struct hdmi_platform_config *config;
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/* audio state: */
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struct hdmi_audio audio;
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/* video state: */
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bool power_on;
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unsigned long int pixclock;
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void __iomem *mmio;
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void __iomem *qfprom_mmio;
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phys_addr_t mmio_phy_addr;
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struct regulator **hpd_regs;
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struct regulator **pwr_regs;
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struct clk **hpd_clks;
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struct clk **pwr_clks;
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struct hdmi_phy *phy;
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struct device *phy_dev;
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struct i2c_adapter *i2c;
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struct drm_connector *connector;
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struct drm_bridge *bridge;
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/* the encoder we are hooked to (outside of hdmi block) */
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struct drm_encoder *encoder;
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bool hdmi_mode; /* are we in hdmi mode? */
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int irq;
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struct workqueue_struct *workq;
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struct hdmi_hdcp_ctrl *hdcp_ctrl;
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/*
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* spinlock to protect registers shared by different execution
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* REG_HDMI_CTRL
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* REG_HDMI_DDC_ARBITRATION
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* REG_HDMI_HDCP_INT_CTRL
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* REG_HDMI_HPD_CTRL
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*/
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spinlock_t reg_lock;
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};
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/* platform config data (ie. from DT, or pdata) */
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struct hdmi_platform_config {
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const char *mmio_name;
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const char *qfprom_mmio_name;
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/* regulators that need to be on for hpd: */
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const char **hpd_reg_names;
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int hpd_reg_cnt;
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/* regulators that need to be on for screen pwr: */
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const char **pwr_reg_names;
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int pwr_reg_cnt;
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/* clks that need to be on for hpd: */
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const char **hpd_clk_names;
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const long unsigned *hpd_freq;
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int hpd_clk_cnt;
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/* clks that need to be on for screen pwr (ie pixel clk): */
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const char **pwr_clk_names;
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int pwr_clk_cnt;
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/* gpio's: */
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struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
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};
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void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
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static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
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{
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msm_writel(data, hdmi->mmio + reg);
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}
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static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
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{
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return msm_readl(hdmi->mmio + reg);
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}
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static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
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{
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return msm_readl(hdmi->qfprom_mmio + reg);
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}
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/*
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* hdmi phy:
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*/
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enum hdmi_phy_type {
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MSM_HDMI_PHY_8x60,
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MSM_HDMI_PHY_8960,
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MSM_HDMI_PHY_8x74,
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MSM_HDMI_PHY_8996,
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MSM_HDMI_PHY_MAX,
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};
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struct hdmi_phy_cfg {
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enum hdmi_phy_type type;
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void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
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void (*powerdown)(struct hdmi_phy *phy);
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const char * const *reg_names;
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int num_regs;
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const char * const *clk_names;
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int num_clks;
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};
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
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struct hdmi_phy {
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struct platform_device *pdev;
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void __iomem *mmio;
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struct hdmi_phy_cfg *cfg;
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const struct hdmi_phy_funcs *funcs;
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struct regulator **regs;
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struct clk **clks;
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};
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static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
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{
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msm_writel(data, phy->mmio + reg);
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}
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static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
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{
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return msm_readl(phy->mmio + reg);
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}
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int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
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void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
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void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
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void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
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void __init msm_hdmi_phy_driver_register(void);
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void __exit msm_hdmi_phy_driver_unregister(void);
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#ifdef CONFIG_COMMON_CLK
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int msm_hdmi_pll_8960_init(struct platform_device *pdev);
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int msm_hdmi_pll_8996_init(struct platform_device *pdev);
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#else
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static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
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{
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return -ENODEV;
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}
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static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
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{
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return -ENODEV;
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}
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#endif
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/*
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* audio:
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*/
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/* Supported HDMI Audio channels and rates */
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#define MSM_HDMI_AUDIO_CHANNEL_2 0
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#define MSM_HDMI_AUDIO_CHANNEL_4 1
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#define MSM_HDMI_AUDIO_CHANNEL_6 2
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#define MSM_HDMI_AUDIO_CHANNEL_8 3
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#define HDMI_SAMPLE_RATE_32KHZ 0
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#define HDMI_SAMPLE_RATE_44_1KHZ 1
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#define HDMI_SAMPLE_RATE_48KHZ 2
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#define HDMI_SAMPLE_RATE_88_2KHZ 3
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#define HDMI_SAMPLE_RATE_96KHZ 4
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#define HDMI_SAMPLE_RATE_176_4KHZ 5
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#define HDMI_SAMPLE_RATE_192KHZ 6
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int msm_hdmi_audio_update(struct hdmi *hdmi);
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int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
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uint32_t num_of_channels, uint32_t channel_allocation,
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uint32_t level_shift, bool down_mix);
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void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
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/*
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* hdmi bridge:
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*/
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struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
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void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
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/*
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* hdmi connector:
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*/
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void msm_hdmi_connector_irq(struct drm_connector *connector);
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struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
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int msm_hdmi_hpd_enable(struct drm_connector *connector);
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/*
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* i2c adapter for ddc:
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*/
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void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
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void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
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struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
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/*
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* hdcp
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*/
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#ifdef CONFIG_DRM_MSM_HDMI_HDCP
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struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
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void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
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void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
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void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
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void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
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#else
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static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
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{
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return ERR_PTR(-ENXIO);
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}
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static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
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static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
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static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
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static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
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#endif
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#endif /* __HDMI_CONNECTOR_H__ */
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