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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
dc30c35be7
The switch can have up to two interrupt controllers. One of these contains the interrupts from the integrated PHYs, so is useful to export. The Marvell PHY driver can then be used in interrupt mode, rather than polling, speeding up PHY handling and reducing load on the MDIO bus. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
629 lines
14 KiB
C
629 lines
14 KiB
C
/*
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* Marvell 88E6xxx Switch Global 2 Registers support (device address
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* 0x1C)
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/irqdomain.h>
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#include "mv88e6xxx.h"
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#include "global2.h"
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#define ADDR_GLOBAL2 0x1c
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static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
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}
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static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
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}
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static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
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{
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return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
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}
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static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
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}
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/* Offset 0x06: Device Mapping Table register */
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static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
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int target, int port)
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{
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u16 val = (target << 8) | (port & 0xf);
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return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val);
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}
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static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
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{
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int target, port;
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int err;
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/* Initialize the routing port to the 32 possible target devices */
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for (target = 0; target < 32; ++target) {
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port = 0xf;
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if (target < DSA_MAX_SWITCHES) {
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port = chip->ds->rtable[target];
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if (port == DSA_RTABLE_NONE)
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port = 0xf;
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}
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err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
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if (err)
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break;
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}
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return err;
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}
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/* Offset 0x07: Trunk Mask Table register */
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static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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bool hask, u16 mask)
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{
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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u16 val = (num << 12) | (mask & port_mask);
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if (hask)
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val |= GLOBAL2_TRUNK_MASK_HASK;
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return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val);
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}
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/* Offset 0x08: Trunk Mapping Table register */
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static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
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u16 map)
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{
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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u16 val = (id << 11) | (map & port_mask);
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return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val);
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}
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static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
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{
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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int i, err;
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/* Clear all eight possible Trunk Mask vectors */
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for (i = 0; i < 8; ++i) {
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err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
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if (err)
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return err;
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}
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/* Clear all sixteen possible Trunk ID routing vectors */
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for (i = 0; i < 16; ++i) {
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err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
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if (err)
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return err;
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}
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return 0;
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}
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/* Offset 0x09: Ingress Rate Command register
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* Offset 0x0A: Ingress Rate Data register
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*/
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static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
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{
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int port, err;
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/* Init all Ingress Rate Limit resources of all ports */
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for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
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/* XXX newer chips (like 88E6390) have different 2-bit ops */
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err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_OP_INIT_ALL |
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(port << 8));
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if (err)
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break;
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/* Wait for the operation to complete */
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err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_BUSY);
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if (err)
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break;
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}
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return err;
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}
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/* Offset 0x0D: Switch MAC/WoL/WoF register */
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static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
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unsigned int pointer, u8 data)
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{
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u16 val = (pointer << 8) | data;
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return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val);
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}
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int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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{
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int i, err;
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for (i = 0; i < 6; i++) {
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err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
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if (err)
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break;
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}
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return err;
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}
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/* Offset 0x0F: Priority Override Table */
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static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
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u8 data)
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{
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u16 val = (pointer << 8) | (data & 0x7);
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return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
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}
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static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
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{
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int i, err;
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/* Clear all sixteen possible Priority Override entries */
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_g2_pot_write(chip, i, 0);
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if (err)
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break;
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}
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return err;
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}
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/* Offset 0x14: EEPROM Command
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* Offset 0x15: EEPROM Data
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*/
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static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD,
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GLOBAL2_EEPROM_CMD_BUSY |
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GLOBAL2_EEPROM_CMD_RUNNING);
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}
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static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
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{
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int err;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd);
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if (err)
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return err;
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return mv88e6xxx_g2_eeprom_wait(chip);
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}
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static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
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u8 addr, u16 *data)
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{
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u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
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int err;
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err = mv88e6xxx_g2_eeprom_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
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if (err)
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return err;
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return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data);
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}
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static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
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u8 addr, u16 data)
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{
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u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
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int err;
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err = mv88e6xxx_g2_eeprom_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data);
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if (err)
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return err;
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return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
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}
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int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
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struct ethtool_eeprom *eeprom, u8 *data)
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{
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unsigned int offset = eeprom->offset;
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unsigned int len = eeprom->len;
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u16 val;
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int err;
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eeprom->len = 0;
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if (offset & 1) {
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err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
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if (err)
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return err;
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*data++ = (val >> 8) & 0xff;
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offset++;
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len--;
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eeprom->len++;
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}
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while (len >= 2) {
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err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
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if (err)
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return err;
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*data++ = val & 0xff;
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*data++ = (val >> 8) & 0xff;
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offset += 2;
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len -= 2;
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eeprom->len += 2;
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}
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if (len) {
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err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
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if (err)
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return err;
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*data++ = val & 0xff;
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offset++;
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len--;
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eeprom->len++;
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}
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return 0;
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}
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int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
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struct ethtool_eeprom *eeprom, u8 *data)
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{
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unsigned int offset = eeprom->offset;
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unsigned int len = eeprom->len;
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u16 val;
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int err;
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/* Ensure the RO WriteEn bit is set */
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err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val);
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if (err)
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return err;
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if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
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return -EROFS;
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eeprom->len = 0;
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if (offset & 1) {
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err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
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if (err)
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return err;
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val = (*data++ << 8) | (val & 0xff);
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err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
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if (err)
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return err;
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offset++;
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len--;
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eeprom->len++;
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}
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while (len >= 2) {
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val = *data++;
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val |= *data++ << 8;
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err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
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if (err)
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return err;
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offset += 2;
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len -= 2;
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eeprom->len += 2;
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}
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if (len) {
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err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
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if (err)
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return err;
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val = (val & 0xff00) | *data++;
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err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
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if (err)
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return err;
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offset++;
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len--;
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eeprom->len++;
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}
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return 0;
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}
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/* Offset 0x18: SMI PHY Command Register
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* Offset 0x19: SMI PHY Data Register
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*/
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static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD,
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GLOBAL2_SMI_PHY_CMD_BUSY);
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}
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static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
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{
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int err;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd);
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if (err)
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return err;
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return mv88e6xxx_g2_smi_phy_wait(chip);
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}
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int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr, int reg,
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u16 *val)
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{
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u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
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int err;
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err = mv88e6xxx_g2_smi_phy_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
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if (err)
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return err;
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return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
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}
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int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg,
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u16 val)
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{
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u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
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int err;
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err = mv88e6xxx_g2_smi_phy_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
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if (err)
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return err;
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return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
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}
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static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
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{
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struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int n = d->hwirq;
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chip->g2_irq.masked |= (1 << n);
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}
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static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
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{
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struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int n = d->hwirq;
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chip->g2_irq.masked &= ~(1 << n);
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}
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static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
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{
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struct mv88e6xxx_chip *chip = dev_id;
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unsigned int nhandled = 0;
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unsigned int sub_irq;
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unsigned int n;
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int err;
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u16 reg;
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mutex_lock(&chip->reg_lock);
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err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®);
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mutex_unlock(&chip->reg_lock);
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if (err)
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goto out;
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for (n = 0; n < 16; ++n) {
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if (reg & (1 << n)) {
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sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
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handle_nested_irq(sub_irq);
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++nhandled;
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}
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}
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out:
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return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
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}
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static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
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{
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struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
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mutex_lock(&chip->reg_lock);
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}
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static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
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{
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struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
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mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
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mutex_unlock(&chip->reg_lock);
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}
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static struct irq_chip mv88e6xxx_g2_irq_chip = {
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.name = "mv88e6xxx-g2",
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.irq_mask = mv88e6xxx_g2_irq_mask,
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.irq_unmask = mv88e6xxx_g2_irq_unmask,
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.irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
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.irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
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};
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static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
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unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct mv88e6xxx_chip *chip = d->host_data;
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irq_set_chip_data(irq, d->host_data);
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irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
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.map = mv88e6xxx_g2_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
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{
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int irq, virq;
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for (irq = 0; irq < 16; irq++) {
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virq = irq_find_mapping(chip->g2_irq.domain, irq);
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irq_dispose_mapping(virq);
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}
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irq_domain_remove(chip->g2_irq.domain);
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}
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int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
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{
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int device_irq;
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int err, irq;
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if (!chip->dev->of_node)
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return -EINVAL;
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chip->g2_irq.domain = irq_domain_add_simple(
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chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
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if (!chip->g2_irq.domain)
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return -ENOMEM;
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for (irq = 0; irq < 16; irq++)
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irq_create_mapping(chip->g2_irq.domain, irq);
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chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
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chip->g2_irq.masked = ~0;
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device_irq = irq_find_mapping(chip->g1_irq.domain,
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GLOBAL_STATUS_IRQ_DEVICE);
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if (device_irq < 0) {
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err = device_irq;
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goto out;
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}
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err = devm_request_threaded_irq(chip->dev, device_irq, NULL,
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mv88e6xxx_g2_irq_thread_fn,
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IRQF_ONESHOT, "mv88e6xxx-g1", chip);
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if (err)
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goto out;
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return 0;
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out:
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mv88e6xxx_g2_irq_free(chip);
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return err;
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}
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int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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{
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u16 reg;
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int err;
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
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/* Consider the frames with reserved multicast destination
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* addresses matching 01:80:c2:00:00:2x as MGMT.
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*/
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err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
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if (err)
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return err;
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}
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
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/* Consider the frames with reserved multicast destination
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* addresses matching 01:80:c2:00:00:0x as MGMT.
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*/
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err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
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if (err)
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return err;
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}
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/* Ignore removed tag data on doubly tagged packets, disable
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* flow control messages, force flow control priority to the
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* highest, and send all special multicast frames to the CPU
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* port at the highest priority.
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*/
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reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
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mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
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reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
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if (err)
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return err;
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/* Program the DSA routing table. */
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err = mv88e6xxx_g2_set_device_mapping(chip);
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if (err)
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return err;
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/* Clear all trunk masks and mapping. */
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err = mv88e6xxx_g2_clear_trunk(chip);
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if (err)
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return err;
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|
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
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/* Disable ingress rate limiting by resetting all per port
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* ingress rate limit resources to their initial state.
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*/
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err = mv88e6xxx_g2_clear_irl(chip);
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if (err)
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return err;
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}
|
|
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
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/* Initialize Cross-chip Port VLAN Table to reset defaults */
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err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR,
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GLOBAL2_PVT_ADDR_OP_INIT_ONES);
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if (err)
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return err;
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}
|
|
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
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/* Clear the priority override table. */
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err = mv88e6xxx_g2_clear_pot(chip);
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if (err)
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return err;
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|
}
|
|
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return 0;
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}
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