mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 01:46:43 +07:00
681ee44d40
We need to fall back from logical-flat APIC mode to physical-flat mode when we have more than 8 CPUs. However, in the presence of CPU hotplug(with bios listing not enabled but possible cpus as disabled cpus in MADT), we have to consider the number of possible CPUs rather than the number of current CPUs; otherwise we may cross the 8-CPU boundary when CPUs are added later. 32bit apic code can use more cleanups (like the removal of vendor checks in 32bit default_setup_apic_routing()) and more unifications with 64bit code. Yinghai has some patches in works already. This patch addresses the boot issue that is reported in the virtualization guest context. [ hpa: incorporated function annotation feedback from Yinghai Lu ] Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <1265767304.2833.19.camel@sbs-t61.sc.intel.com> Acked-by: Shaohui Zheng <shaohui.zheng@intel.com> Reviewed-by: Yinghai Lu <yinghai@kernel.org> Cc: <stable@kernel.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
1026 lines
24 KiB
C
1026 lines
24 KiB
C
/*
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* Intel Multiprocessor Specification 1.1 and 1.4
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* compliant MP-table parsing routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
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* (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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* (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/pci.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/pgalloc.h>
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#include <asm/io_apic.h>
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#include <asm/proto.h>
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#include <asm/bios_ebda.h>
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#include <asm/e820.h>
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#include <asm/trampoline.h>
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#include <asm/setup.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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/*
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* Checksum an MP configuration block.
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*/
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static int __init mpf_checksum(unsigned char *mp, int len)
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{
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int sum = 0;
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while (len--)
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sum += *mp++;
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return sum & 0xFF;
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}
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int __init default_mpc_apic_id(struct mpc_cpu *m)
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{
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return m->apicid;
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}
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static void __init MP_processor_info(struct mpc_cpu *m)
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{
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int apicid;
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char *bootup_cpu = "";
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if (!(m->cpuflag & CPU_ENABLED)) {
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disabled_cpus++;
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return;
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}
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apicid = x86_init.mpparse.mpc_apic_id(m);
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if (m->cpuflag & CPU_BOOTPROCESSOR) {
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bootup_cpu = " (Bootup-CPU)";
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boot_cpu_physical_apicid = m->apicid;
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}
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printk(KERN_INFO "Processor #%d%s\n", m->apicid, bootup_cpu);
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generic_processor_info(apicid, m->apicver);
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}
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#ifdef CONFIG_X86_IO_APIC
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void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str)
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{
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memcpy(str, m->bustype, 6);
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str[6] = 0;
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apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str);
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}
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static void __init MP_bus_info(struct mpc_bus *m)
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{
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char str[7];
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x86_init.mpparse.mpc_oem_bus_info(m, str);
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#if MAX_MP_BUSSES < 256
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if (m->busid >= MAX_MP_BUSSES) {
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printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
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" is too large, max. supported is %d\n",
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m->busid, str, MAX_MP_BUSSES - 1);
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return;
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}
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#endif
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if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
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set_bit(m->busid, mp_bus_not_pci);
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#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
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mp_bus_id_to_type[m->busid] = MP_BUS_ISA;
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#endif
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} else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
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if (x86_init.mpparse.mpc_oem_pci_bus)
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x86_init.mpparse.mpc_oem_pci_bus(m);
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clear_bit(m->busid, mp_bus_not_pci);
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#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
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mp_bus_id_to_type[m->busid] = MP_BUS_PCI;
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} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
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mp_bus_id_to_type[m->busid] = MP_BUS_EISA;
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} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
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mp_bus_id_to_type[m->busid] = MP_BUS_MCA;
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#endif
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} else
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printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
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}
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static int bad_ioapic(unsigned long address)
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{
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if (nr_ioapics >= MAX_IO_APICS) {
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printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
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"(found %d)\n", MAX_IO_APICS, nr_ioapics);
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panic("Recompile kernel with bigger MAX_IO_APICS!\n");
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}
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if (!address) {
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printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
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" found in table, skipping!\n");
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return 1;
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}
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return 0;
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}
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static void __init MP_ioapic_info(struct mpc_ioapic *m)
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{
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if (!(m->flags & MPC_APIC_USABLE))
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return;
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printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
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m->apicid, m->apicver, m->apicaddr);
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if (bad_ioapic(m->apicaddr))
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return;
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mp_ioapics[nr_ioapics].apicaddr = m->apicaddr;
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mp_ioapics[nr_ioapics].apicid = m->apicid;
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mp_ioapics[nr_ioapics].type = m->type;
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mp_ioapics[nr_ioapics].apicver = m->apicver;
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mp_ioapics[nr_ioapics].flags = m->flags;
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nr_ioapics++;
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}
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static void print_MP_intsrc_info(struct mpc_intsrc *m)
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{
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apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
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m->srcbusirq, m->dstapic, m->dstirq);
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}
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static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
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{
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apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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mp_irq->irqtype, mp_irq->irqflag & 3,
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(mp_irq->irqflag >> 2) & 3, mp_irq->srcbus,
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mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
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}
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static void __init assign_to_mp_irq(struct mpc_intsrc *m,
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struct mpc_intsrc *mp_irq)
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{
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mp_irq->dstapic = m->dstapic;
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mp_irq->type = m->type;
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mp_irq->irqtype = m->irqtype;
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mp_irq->irqflag = m->irqflag;
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mp_irq->srcbus = m->srcbus;
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mp_irq->srcbusirq = m->srcbusirq;
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mp_irq->dstirq = m->dstirq;
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}
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static void __init assign_to_mpc_intsrc(struct mpc_intsrc *mp_irq,
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struct mpc_intsrc *m)
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{
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m->dstapic = mp_irq->dstapic;
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m->type = mp_irq->type;
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m->irqtype = mp_irq->irqtype;
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m->irqflag = mp_irq->irqflag;
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m->srcbus = mp_irq->srcbus;
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m->srcbusirq = mp_irq->srcbusirq;
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m->dstirq = mp_irq->dstirq;
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}
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static int __init mp_irq_mpc_intsrc_cmp(struct mpc_intsrc *mp_irq,
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struct mpc_intsrc *m)
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{
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if (mp_irq->dstapic != m->dstapic)
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return 1;
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if (mp_irq->type != m->type)
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return 2;
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if (mp_irq->irqtype != m->irqtype)
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return 3;
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if (mp_irq->irqflag != m->irqflag)
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return 4;
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if (mp_irq->srcbus != m->srcbus)
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return 5;
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if (mp_irq->srcbusirq != m->srcbusirq)
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return 6;
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if (mp_irq->dstirq != m->dstirq)
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return 7;
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return 0;
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}
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static void __init MP_intsrc_info(struct mpc_intsrc *m)
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{
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int i;
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print_MP_intsrc_info(m);
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for (i = 0; i < mp_irq_entries; i++) {
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if (!mp_irq_mpc_intsrc_cmp(&mp_irqs[i], m))
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return;
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}
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assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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#else /* CONFIG_X86_IO_APIC */
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static inline void __init MP_bus_info(struct mpc_bus *m) {}
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static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
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static inline void __init MP_intsrc_info(struct mpc_intsrc *m) {}
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#endif /* CONFIG_X86_IO_APIC */
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static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
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{
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apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x,"
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" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
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m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid,
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m->srcbusirq, m->destapic, m->destapiclint);
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}
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/*
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* Read/parse the MPC
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*/
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static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
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{
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if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {
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printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
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mpc->signature[0], mpc->signature[1],
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mpc->signature[2], mpc->signature[3]);
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return 0;
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}
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if (mpf_checksum((unsigned char *)mpc, mpc->length)) {
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printk(KERN_ERR "MPTABLE: checksum error!\n");
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return 0;
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}
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if (mpc->spec != 0x01 && mpc->spec != 0x04) {
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printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
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mpc->spec);
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return 0;
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}
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if (!mpc->lapic) {
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printk(KERN_ERR "MPTABLE: null local APIC address!\n");
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return 0;
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}
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memcpy(oem, mpc->oem, 8);
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oem[8] = 0;
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printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem);
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memcpy(str, mpc->productid, 12);
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str[12] = 0;
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printk(KERN_INFO "MPTABLE: Product ID: %s\n", str);
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printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->lapic);
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return 1;
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}
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static void skip_entry(unsigned char **ptr, int *count, int size)
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{
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*ptr += size;
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*count += size;
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}
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static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
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{
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printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n"
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"type %x\n", *mpt);
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print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
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1, mpc, mpc->length, 1);
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}
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void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { }
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static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
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{
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char str[16];
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char oem[10];
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int count = sizeof(*mpc);
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unsigned char *mpt = ((unsigned char *)mpc) + count;
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if (!smp_check_mpc(mpc, oem, str))
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return 0;
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#ifdef CONFIG_X86_32
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generic_mps_oem_check(mpc, oem, str);
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#endif
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/* save the local APIC address, it might be non-default */
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if (!acpi_lapic)
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mp_lapic_addr = mpc->lapic;
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if (early)
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return 1;
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if (mpc->oemptr)
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x86_init.mpparse.smp_read_mpc_oem(mpc);
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/*
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* Now process the configuration blocks.
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*/
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x86_init.mpparse.mpc_record(0);
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while (count < mpc->length) {
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switch (*mpt) {
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case MP_PROCESSOR:
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/* ACPI may have already provided this data */
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if (!acpi_lapic)
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MP_processor_info((struct mpc_cpu *)mpt);
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skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
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break;
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case MP_BUS:
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MP_bus_info((struct mpc_bus *)mpt);
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skip_entry(&mpt, &count, sizeof(struct mpc_bus));
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break;
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case MP_IOAPIC:
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MP_ioapic_info((struct mpc_ioapic *)mpt);
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skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
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break;
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case MP_INTSRC:
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MP_intsrc_info((struct mpc_intsrc *)mpt);
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skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
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break;
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case MP_LINTSRC:
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MP_lintsrc_info((struct mpc_lintsrc *)mpt);
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skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
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break;
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default:
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/* wrong mptable */
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smp_dump_mptable(mpc, mpt);
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count = mpc->length;
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break;
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}
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x86_init.mpparse.mpc_record(1);
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}
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if (!num_processors)
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printk(KERN_ERR "MPTABLE: no processors registered!\n");
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return num_processors;
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}
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#ifdef CONFIG_X86_IO_APIC
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static int __init ELCR_trigger(unsigned int irq)
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{
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unsigned int port;
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port = 0x4d0 + (irq >> 3);
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return (inb(port) >> (irq & 7)) & 1;
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}
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static void __init construct_default_ioirq_mptable(int mpc_default_type)
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{
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struct mpc_intsrc intsrc;
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int i;
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int ELCR_fallback = 0;
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intsrc.type = MP_INTSRC;
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intsrc.irqflag = 0; /* conforming */
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intsrc.srcbus = 0;
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intsrc.dstapic = mp_ioapics[0].apicid;
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intsrc.irqtype = mp_INT;
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/*
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* If true, we have an ISA/PCI system with no IRQ entries
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* in the MP table. To prevent the PCI interrupts from being set up
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* incorrectly, we try to use the ELCR. The sanity check to see if
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* there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
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* never be level sensitive, so we simply see if the ELCR agrees.
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* If it does, we assume it's valid.
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*/
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if (mpc_default_type == 5) {
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printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
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"falling back to ELCR\n");
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if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
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ELCR_trigger(13))
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printk(KERN_ERR "ELCR contains invalid data... "
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"not using ELCR\n");
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else {
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printk(KERN_INFO
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"Using ELCR to identify PCI interrupts\n");
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ELCR_fallback = 1;
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}
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}
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for (i = 0; i < 16; i++) {
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switch (mpc_default_type) {
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case 2:
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if (i == 0 || i == 13)
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continue; /* IRQ0 & IRQ13 not connected */
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/* fall through */
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default:
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if (i == 2)
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continue; /* IRQ2 is never connected */
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}
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if (ELCR_fallback) {
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/*
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* If the ELCR indicates a level-sensitive interrupt, we
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* copy that information over to the MP table in the
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* irqflag field (level sensitive, active high polarity).
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*/
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if (ELCR_trigger(i))
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intsrc.irqflag = 13;
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else
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intsrc.irqflag = 0;
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}
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intsrc.srcbusirq = i;
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intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
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MP_intsrc_info(&intsrc);
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}
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intsrc.irqtype = mp_ExtINT;
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intsrc.srcbusirq = 0;
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intsrc.dstirq = 0; /* 8259A to INTIN0 */
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MP_intsrc_info(&intsrc);
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}
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static void __init construct_ioapic_table(int mpc_default_type)
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{
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struct mpc_ioapic ioapic;
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struct mpc_bus bus;
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bus.type = MP_BUS;
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bus.busid = 0;
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switch (mpc_default_type) {
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default:
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printk(KERN_ERR "???\nUnknown standard configuration %d\n",
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mpc_default_type);
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/* fall through */
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case 1:
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case 5:
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memcpy(bus.bustype, "ISA ", 6);
|
|
break;
|
|
case 2:
|
|
case 6:
|
|
case 3:
|
|
memcpy(bus.bustype, "EISA ", 6);
|
|
break;
|
|
case 4:
|
|
case 7:
|
|
memcpy(bus.bustype, "MCA ", 6);
|
|
}
|
|
MP_bus_info(&bus);
|
|
if (mpc_default_type > 4) {
|
|
bus.busid = 1;
|
|
memcpy(bus.bustype, "PCI ", 6);
|
|
MP_bus_info(&bus);
|
|
}
|
|
|
|
ioapic.type = MP_IOAPIC;
|
|
ioapic.apicid = 2;
|
|
ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
|
ioapic.flags = MPC_APIC_USABLE;
|
|
ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE;
|
|
MP_ioapic_info(&ioapic);
|
|
|
|
/*
|
|
* We set up most of the low 16 IO-APIC pins according to MPS rules.
|
|
*/
|
|
construct_default_ioirq_mptable(mpc_default_type);
|
|
}
|
|
#else
|
|
static inline void __init construct_ioapic_table(int mpc_default_type) { }
|
|
#endif
|
|
|
|
static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
|
{
|
|
struct mpc_cpu processor;
|
|
struct mpc_lintsrc lintsrc;
|
|
int linttypes[2] = { mp_ExtINT, mp_NMI };
|
|
int i;
|
|
|
|
/*
|
|
* local APIC has default address
|
|
*/
|
|
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
|
|
|
/*
|
|
* 2 CPUs, numbered 0 & 1.
|
|
*/
|
|
processor.type = MP_PROCESSOR;
|
|
/* Either an integrated APIC or a discrete 82489DX. */
|
|
processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
|
processor.cpuflag = CPU_ENABLED;
|
|
processor.cpufeature = (boot_cpu_data.x86 << 8) |
|
|
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
|
|
processor.featureflag = boot_cpu_data.x86_capability[0];
|
|
processor.reserved[0] = 0;
|
|
processor.reserved[1] = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
processor.apicid = i;
|
|
MP_processor_info(&processor);
|
|
}
|
|
|
|
construct_ioapic_table(mpc_default_type);
|
|
|
|
lintsrc.type = MP_LINTSRC;
|
|
lintsrc.irqflag = 0; /* conforming */
|
|
lintsrc.srcbusid = 0;
|
|
lintsrc.srcbusirq = 0;
|
|
lintsrc.destapic = MP_APIC_ALL;
|
|
for (i = 0; i < 2; i++) {
|
|
lintsrc.irqtype = linttypes[i];
|
|
lintsrc.destapiclint = i;
|
|
MP_lintsrc_info(&lintsrc);
|
|
}
|
|
}
|
|
|
|
static struct mpf_intel *mpf_found;
|
|
|
|
static unsigned long __init get_mpc_size(unsigned long physptr)
|
|
{
|
|
struct mpc_table *mpc;
|
|
unsigned long size;
|
|
|
|
mpc = early_ioremap(physptr, PAGE_SIZE);
|
|
size = mpc->length;
|
|
early_iounmap(mpc, PAGE_SIZE);
|
|
apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size);
|
|
|
|
return size;
|
|
}
|
|
|
|
static int __init check_physptr(struct mpf_intel *mpf, unsigned int early)
|
|
{
|
|
struct mpc_table *mpc;
|
|
unsigned long size;
|
|
|
|
size = get_mpc_size(mpf->physptr);
|
|
mpc = early_ioremap(mpf->physptr, size);
|
|
/*
|
|
* Read the physical hardware table. Anything here will
|
|
* override the defaults.
|
|
*/
|
|
if (!smp_read_mpc(mpc, early)) {
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
smp_found_config = 0;
|
|
#endif
|
|
printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"
|
|
"... disabling SMP support. (tell your hw vendor)\n");
|
|
early_iounmap(mpc, size);
|
|
return -1;
|
|
}
|
|
early_iounmap(mpc, size);
|
|
|
|
if (early)
|
|
return -1;
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
/*
|
|
* If there are no explicit MP IRQ entries, then we are
|
|
* broken. We set up most of the low 16 IO-APIC pins to
|
|
* ISA defaults and hope it will work.
|
|
*/
|
|
if (!mp_irq_entries) {
|
|
struct mpc_bus bus;
|
|
|
|
printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
|
|
"using default mptable. (tell your hw vendor)\n");
|
|
|
|
bus.type = MP_BUS;
|
|
bus.busid = 0;
|
|
memcpy(bus.bustype, "ISA ", 6);
|
|
MP_bus_info(&bus);
|
|
|
|
construct_default_ioirq_mptable(0);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Scan the memory blocks for an SMP configuration block.
|
|
*/
|
|
void __init default_get_smp_config(unsigned int early)
|
|
{
|
|
struct mpf_intel *mpf = mpf_found;
|
|
|
|
if (!mpf)
|
|
return;
|
|
|
|
if (acpi_lapic && early)
|
|
return;
|
|
|
|
/*
|
|
* MPS doesn't support hyperthreading, aka only have
|
|
* thread 0 apic id in MPS table
|
|
*/
|
|
if (acpi_lapic && acpi_ioapic)
|
|
return;
|
|
|
|
printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
|
|
mpf->specification);
|
|
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
|
|
if (mpf->feature2 & (1 << 7)) {
|
|
printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
|
|
pic_mode = 1;
|
|
} else {
|
|
printk(KERN_INFO " Virtual Wire compatibility mode.\n");
|
|
pic_mode = 0;
|
|
}
|
|
#endif
|
|
/*
|
|
* Now see if we need to read further.
|
|
*/
|
|
if (mpf->feature1 != 0) {
|
|
if (early) {
|
|
/*
|
|
* local APIC has default address
|
|
*/
|
|
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
|
return;
|
|
}
|
|
|
|
printk(KERN_INFO "Default MP configuration #%d\n",
|
|
mpf->feature1);
|
|
construct_default_ISA_mptable(mpf->feature1);
|
|
|
|
} else if (mpf->physptr) {
|
|
if (check_physptr(mpf, early))
|
|
return;
|
|
} else
|
|
BUG();
|
|
|
|
if (!early)
|
|
printk(KERN_INFO "Processors: %d\n", num_processors);
|
|
/*
|
|
* Only use the first configuration found.
|
|
*/
|
|
}
|
|
|
|
static void __init smp_reserve_memory(struct mpf_intel *mpf)
|
|
{
|
|
unsigned long size = get_mpc_size(mpf->physptr);
|
|
|
|
reserve_early(mpf->physptr, mpf->physptr+size, "MP-table mpc");
|
|
}
|
|
|
|
static int __init smp_scan_config(unsigned long base, unsigned long length)
|
|
{
|
|
unsigned int *bp = phys_to_virt(base);
|
|
struct mpf_intel *mpf;
|
|
unsigned long mem;
|
|
|
|
apic_printk(APIC_VERBOSE, "Scan SMP from %p for %ld bytes.\n",
|
|
bp, length);
|
|
BUILD_BUG_ON(sizeof(*mpf) != 16);
|
|
|
|
while (length > 0) {
|
|
mpf = (struct mpf_intel *)bp;
|
|
if ((*bp == SMP_MAGIC_IDENT) &&
|
|
(mpf->length == 1) &&
|
|
!mpf_checksum((unsigned char *)bp, 16) &&
|
|
((mpf->specification == 1)
|
|
|| (mpf->specification == 4))) {
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
smp_found_config = 1;
|
|
#endif
|
|
mpf_found = mpf;
|
|
|
|
printk(KERN_INFO "found SMP MP-table at [%p] %llx\n",
|
|
mpf, (u64)virt_to_phys(mpf));
|
|
|
|
mem = virt_to_phys(mpf);
|
|
reserve_early(mem, mem + sizeof(*mpf), "MP-table mpf");
|
|
if (mpf->physptr)
|
|
smp_reserve_memory(mpf);
|
|
|
|
return 1;
|
|
}
|
|
bp += 4;
|
|
length -= 16;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void __init default_find_smp_config(void)
|
|
{
|
|
unsigned int address;
|
|
|
|
/*
|
|
* FIXME: Linux assumes you have 640K of base ram..
|
|
* this continues the error...
|
|
*
|
|
* 1) Scan the bottom 1K for a signature
|
|
* 2) Scan the top 1K of base RAM
|
|
* 3) Scan the 64K of bios
|
|
*/
|
|
if (smp_scan_config(0x0, 0x400) ||
|
|
smp_scan_config(639 * 0x400, 0x400) ||
|
|
smp_scan_config(0xF0000, 0x10000))
|
|
return;
|
|
/*
|
|
* If it is an SMP machine we should know now, unless the
|
|
* configuration is in an EISA/MCA bus machine with an
|
|
* extended bios data area.
|
|
*
|
|
* there is a real-mode segmented pointer pointing to the
|
|
* 4K EBDA area at 0x40E, calculate and scan it here.
|
|
*
|
|
* NOTE! There are Linux loaders that will corrupt the EBDA
|
|
* area, and as such this kind of SMP config may be less
|
|
* trustworthy, simply because the SMP table may have been
|
|
* stomped on during early boot. These loaders are buggy and
|
|
* should be fixed.
|
|
*
|
|
* MP1.4 SPEC states to only scan first 1K of 4K EBDA.
|
|
*/
|
|
|
|
address = get_bios_ebda();
|
|
if (address)
|
|
smp_scan_config(address, 0x400);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
static u8 __initdata irq_used[MAX_IRQ_SOURCES];
|
|
|
|
static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
|
|
{
|
|
int i;
|
|
|
|
if (m->irqtype != mp_INT)
|
|
return 0;
|
|
|
|
if (m->irqflag != 0x0f)
|
|
return 0;
|
|
|
|
/* not legacy */
|
|
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
if (mp_irqs[i].irqtype != mp_INT)
|
|
continue;
|
|
|
|
if (mp_irqs[i].irqflag != 0x0f)
|
|
continue;
|
|
|
|
if (mp_irqs[i].srcbus != m->srcbus)
|
|
continue;
|
|
if (mp_irqs[i].srcbusirq != m->srcbusirq)
|
|
continue;
|
|
if (irq_used[i]) {
|
|
/* already claimed */
|
|
return -2;
|
|
}
|
|
irq_used[i] = 1;
|
|
return i;
|
|
}
|
|
|
|
/* not found */
|
|
return -1;
|
|
}
|
|
|
|
#define SPARE_SLOT_NUM 20
|
|
|
|
static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM];
|
|
|
|
static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
|
|
{
|
|
int i;
|
|
|
|
apic_printk(APIC_VERBOSE, "OLD ");
|
|
print_MP_intsrc_info(m);
|
|
|
|
i = get_MP_intsrc_index(m);
|
|
if (i > 0) {
|
|
assign_to_mpc_intsrc(&mp_irqs[i], m);
|
|
apic_printk(APIC_VERBOSE, "NEW ");
|
|
print_mp_irq_info(&mp_irqs[i]);
|
|
return;
|
|
}
|
|
if (!i) {
|
|
/* legacy, do nothing */
|
|
return;
|
|
}
|
|
if (*nr_m_spare < SPARE_SLOT_NUM) {
|
|
/*
|
|
* not found (-1), or duplicated (-2) are invalid entries,
|
|
* we need to use the slot later
|
|
*/
|
|
m_spare[*nr_m_spare] = m;
|
|
*nr_m_spare += 1;
|
|
}
|
|
}
|
|
#else /* CONFIG_X86_IO_APIC */
|
|
static
|
|
inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {}
|
|
#endif /* CONFIG_X86_IO_APIC */
|
|
|
|
static int
|
|
check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!mpc_new_phys || count <= mpc_new_length) {
|
|
WARN(1, "update_mptable: No spare slots (length: %x)\n", count);
|
|
return -1;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init replace_intsrc_all(struct mpc_table *mpc,
|
|
unsigned long mpc_new_phys,
|
|
unsigned long mpc_new_length)
|
|
{
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
int i;
|
|
#endif
|
|
int count = sizeof(*mpc);
|
|
int nr_m_spare = 0;
|
|
unsigned char *mpt = ((unsigned char *)mpc) + count;
|
|
|
|
printk(KERN_INFO "mpc_length %x\n", mpc->length);
|
|
while (count < mpc->length) {
|
|
switch (*mpt) {
|
|
case MP_PROCESSOR:
|
|
skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
|
|
break;
|
|
case MP_BUS:
|
|
skip_entry(&mpt, &count, sizeof(struct mpc_bus));
|
|
break;
|
|
case MP_IOAPIC:
|
|
skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
|
|
break;
|
|
case MP_INTSRC:
|
|
check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare);
|
|
skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
|
|
break;
|
|
case MP_LINTSRC:
|
|
skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
|
|
break;
|
|
default:
|
|
/* wrong mptable */
|
|
smp_dump_mptable(mpc, mpt);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
if (irq_used[i])
|
|
continue;
|
|
|
|
if (mp_irqs[i].irqtype != mp_INT)
|
|
continue;
|
|
|
|
if (mp_irqs[i].irqflag != 0x0f)
|
|
continue;
|
|
|
|
if (nr_m_spare > 0) {
|
|
apic_printk(APIC_VERBOSE, "*NEW* found\n");
|
|
nr_m_spare--;
|
|
assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]);
|
|
m_spare[nr_m_spare] = NULL;
|
|
} else {
|
|
struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
|
|
count += sizeof(struct mpc_intsrc);
|
|
if (check_slot(mpc_new_phys, mpc_new_length, count) < 0)
|
|
goto out;
|
|
assign_to_mpc_intsrc(&mp_irqs[i], m);
|
|
mpc->length = count;
|
|
mpt += sizeof(struct mpc_intsrc);
|
|
}
|
|
print_mp_irq_info(&mp_irqs[i]);
|
|
}
|
|
#endif
|
|
out:
|
|
/* update checksum */
|
|
mpc->checksum = 0;
|
|
mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int enable_update_mptable;
|
|
|
|
static int __init update_mptable_setup(char *str)
|
|
{
|
|
enable_update_mptable = 1;
|
|
#ifdef CONFIG_PCI
|
|
pci_routeirq = 1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
early_param("update_mptable", update_mptable_setup);
|
|
|
|
static unsigned long __initdata mpc_new_phys;
|
|
static unsigned long mpc_new_length __initdata = 4096;
|
|
|
|
/* alloc_mptable or alloc_mptable=4k */
|
|
static int __initdata alloc_mptable;
|
|
static int __init parse_alloc_mptable_opt(char *p)
|
|
{
|
|
enable_update_mptable = 1;
|
|
#ifdef CONFIG_PCI
|
|
pci_routeirq = 1;
|
|
#endif
|
|
alloc_mptable = 1;
|
|
if (!p)
|
|
return 0;
|
|
mpc_new_length = memparse(p, &p);
|
|
return 0;
|
|
}
|
|
early_param("alloc_mptable", parse_alloc_mptable_opt);
|
|
|
|
void __init early_reserve_e820_mpc_new(void)
|
|
{
|
|
if (enable_update_mptable && alloc_mptable) {
|
|
u64 startt = 0;
|
|
mpc_new_phys = early_reserve_e820(startt, mpc_new_length, 4);
|
|
}
|
|
}
|
|
|
|
static int __init update_mp_table(void)
|
|
{
|
|
char str[16];
|
|
char oem[10];
|
|
struct mpf_intel *mpf;
|
|
struct mpc_table *mpc, *mpc_new;
|
|
|
|
if (!enable_update_mptable)
|
|
return 0;
|
|
|
|
mpf = mpf_found;
|
|
if (!mpf)
|
|
return 0;
|
|
|
|
/*
|
|
* Now see if we need to go further.
|
|
*/
|
|
if (mpf->feature1 != 0)
|
|
return 0;
|
|
|
|
if (!mpf->physptr)
|
|
return 0;
|
|
|
|
mpc = phys_to_virt(mpf->physptr);
|
|
|
|
if (!smp_check_mpc(mpc, oem, str))
|
|
return 0;
|
|
|
|
printk(KERN_INFO "mpf: %llx\n", (u64)virt_to_phys(mpf));
|
|
printk(KERN_INFO "physptr: %x\n", mpf->physptr);
|
|
|
|
if (mpc_new_phys && mpc->length > mpc_new_length) {
|
|
mpc_new_phys = 0;
|
|
printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n",
|
|
mpc_new_length);
|
|
}
|
|
|
|
if (!mpc_new_phys) {
|
|
unsigned char old, new;
|
|
/* check if we can change the postion */
|
|
mpc->checksum = 0;
|
|
old = mpf_checksum((unsigned char *)mpc, mpc->length);
|
|
mpc->checksum = 0xff;
|
|
new = mpf_checksum((unsigned char *)mpc, mpc->length);
|
|
if (old == new) {
|
|
printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n");
|
|
return 0;
|
|
}
|
|
printk(KERN_INFO "use in-positon replacing\n");
|
|
} else {
|
|
mpf->physptr = mpc_new_phys;
|
|
mpc_new = phys_to_virt(mpc_new_phys);
|
|
memcpy(mpc_new, mpc, mpc->length);
|
|
mpc = mpc_new;
|
|
/* check if we can modify that */
|
|
if (mpc_new_phys - mpf->physptr) {
|
|
struct mpf_intel *mpf_new;
|
|
/* steal 16 bytes from [0, 1k) */
|
|
printk(KERN_INFO "mpf new: %x\n", 0x400 - 16);
|
|
mpf_new = phys_to_virt(0x400 - 16);
|
|
memcpy(mpf_new, mpf, 16);
|
|
mpf = mpf_new;
|
|
mpf->physptr = mpc_new_phys;
|
|
}
|
|
mpf->checksum = 0;
|
|
mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16);
|
|
printk(KERN_INFO "physptr new: %x\n", mpf->physptr);
|
|
}
|
|
|
|
/*
|
|
* only replace the one with mp_INT and
|
|
* MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
|
* already in mp_irqs , stored by ... and mp_config_acpi_gsi,
|
|
* may need pci=routeirq for all coverage
|
|
*/
|
|
replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(update_mp_table);
|