mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 04:56:41 +07:00
1b4c5a6e6b
If one adds gpio-controller; to the chip in the devicetree, then initialization fails with 'gpiochip_find_base: cannot find free range', because ngpio is 0. This patch fixes the bug. This version includes the suggestions from Linus Walleij. Tested on ml507 board. Signed-off-by: Gernot Vormayr <gvormayr@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
317 lines
9.2 KiB
C
317 lines
9.2 KiB
C
/*
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* Xilinx gpio driver for xps/axi_gpio IP.
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*
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* Copyright 2008 - 2013 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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/* Register Offset Definitions */
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
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#define XGPIO_CHANNEL_OFFSET 0x8
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/* Read/Write access to the GPIO registers */
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#ifdef CONFIG_ARCH_ZYNQ
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# define xgpio_readreg(offset) readl(offset)
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# define xgpio_writereg(offset, val) writel(val, offset)
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#else
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# define xgpio_readreg(offset) __raw_readl(offset)
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# define xgpio_writereg(offset, val) __raw_writel(val, offset)
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#endif
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/**
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* struct xgpio_instance - Stores information about GPIO device
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* struct of_mm_gpio_chip mmchip: OF GPIO chip for memory mapped banks
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* gpio_state: GPIO state shadow register
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* gpio_dir: GPIO direction shadow register
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* offset: GPIO channel offset
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* gpio_lock: Lock used for synchronization
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*/
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struct xgpio_instance {
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struct of_mm_gpio_chip mmchip;
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u32 gpio_state;
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u32 gpio_dir;
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u32 offset;
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spinlock_t gpio_lock;
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};
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/**
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* xgpio_get - Read the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* This function reads the specified signal of the GPIO device. It returns 0 if
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* the signal clear, 1 if signal is set or negative value on error.
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*/
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs + chip->offset;
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return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) & BIT(gpio));
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}
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/**
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* xgpio_set - Write the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function writes the specified value in to the specified signal of the
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* GPIO device.
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*/
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static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write to GPIO signal and set its direction to output */
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if (val)
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chip->gpio_state |= BIT(gpio);
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else
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chip->gpio_state &= ~BIT(gpio);
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xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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/**
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* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* This function sets the direction of specified GPIO signal as input.
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* It returns 0 if direction of GPIO signals is set as input otherwise it
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* returns negative error value.
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*/
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static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Set the GPIO bit in shadow register and set direction as input */
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chip->gpio_dir |= BIT(gpio);
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xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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return 0;
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}
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/**
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* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function sets the direction of specified GPIO signal as output. If all
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* GPIO signals of GPIO chip is configured as input then it returns
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* error otherwise it returns 0.
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*/
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static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write state of GPIO signal */
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if (val)
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chip->gpio_state |= BIT(gpio);
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else
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chip->gpio_state &= ~BIT(gpio);
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xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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/* Clear the GPIO bit in shadow register and set direction as output */
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chip->gpio_dir &= ~BIT(gpio);
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xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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return 0;
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}
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/**
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* xgpio_save_regs - Set initial values of GPIO pins
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* @mm_gc: pointer to memory mapped GPIO chip structure
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*/
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static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
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chip->gpio_dir);
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}
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/**
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* xgpio_of_probe - Probe method for the GPIO device.
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* @np: pointer to device tree node
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*
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* This function probes the GPIO device in the device tree. It initializes the
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* driver data structure. It returns 0, if the driver is bound to the GPIO
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* device, or a negative value if there is an error.
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*/
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static int xgpio_of_probe(struct device_node *np)
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{
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struct xgpio_instance *chip;
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int status = 0;
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const u32 *tree_info;
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u32 ngpio;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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/* Update GPIO state shadow register with default value */
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of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state);
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/* By default, all pins are inputs */
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chip->gpio_dir = 0xFFFFFFFF;
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/* Update GPIO direction shadow register with default value */
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of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir);
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/*
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* Check device node and parent device node for device width
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* and assume default width of 32
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*/
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if (of_property_read_u32(np, "xlnx,gpio-width", &ngpio))
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ngpio = 32;
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chip->mmchip.gc.ngpio = (u16)ngpio;
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spin_lock_init(&chip->gpio_lock);
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chip->mmchip.gc.direction_input = xgpio_dir_in;
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chip->mmchip.gc.direction_output = xgpio_dir_out;
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chip->mmchip.gc.get = xgpio_get;
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chip->mmchip.gc.set = xgpio_set;
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chip->mmchip.save_regs = xgpio_save_regs;
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/* Call the OF gpio helper to setup and register the GPIO device */
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status = of_mm_gpiochip_add(np, &chip->mmchip);
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if (status) {
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kfree(chip);
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pr_err("%s: error in probe function with status %d\n",
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np->full_name, status);
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return status;
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}
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pr_info("XGpio: %s: registered, base is %d\n", np->full_name,
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chip->mmchip.gc.base);
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tree_info = of_get_property(np, "xlnx,is-dual", NULL);
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if (tree_info && be32_to_cpup(tree_info)) {
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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/* Add dual channel offset */
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chip->offset = XGPIO_CHANNEL_OFFSET;
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/* Update GPIO state shadow register with default value */
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of_property_read_u32(np, "xlnx,dout-default-2",
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&chip->gpio_state);
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/* By default, all pins are inputs */
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chip->gpio_dir = 0xFFFFFFFF;
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/* Update GPIO direction shadow register with default value */
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of_property_read_u32(np, "xlnx,tri-default-2", &chip->gpio_dir);
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/*
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* Check device node and parent device node for device width
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* and assume default width of 32
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*/
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if (of_property_read_u32(np, "xlnx,gpio2-width", &ngpio))
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ngpio = 32;
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chip->mmchip.gc.ngpio = (u16)ngpio;
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spin_lock_init(&chip->gpio_lock);
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chip->mmchip.gc.direction_input = xgpio_dir_in;
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chip->mmchip.gc.direction_output = xgpio_dir_out;
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chip->mmchip.gc.get = xgpio_get;
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chip->mmchip.gc.set = xgpio_set;
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chip->mmchip.save_regs = xgpio_save_regs;
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/* Call the OF gpio helper to setup and register the GPIO dev */
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status = of_mm_gpiochip_add(np, &chip->mmchip);
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if (status) {
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kfree(chip);
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pr_err("%s: error in probe function with status %d\n",
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np->full_name, status);
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return status;
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}
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pr_info("XGpio: %s: dual channel registered, base is %d\n",
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np->full_name, chip->mmchip.gc.base);
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}
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return 0;
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}
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static const struct of_device_id xgpio_of_match[] = {
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{ .compatible = "xlnx,xps-gpio-1.00.a", },
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{ /* end of list */ },
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};
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static int __init xgpio_init(void)
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{
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struct device_node *np;
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for_each_matching_node(np, xgpio_of_match)
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xgpio_of_probe(np);
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return 0;
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}
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/* Make sure we get initialized before anyone else tries to use us */
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subsys_initcall(xgpio_init);
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/* No exit call at the moment as we cannot unregister of GPIO chips */
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MODULE_AUTHOR("Xilinx, Inc.");
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MODULE_DESCRIPTION("Xilinx GPIO driver");
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MODULE_LICENSE("GPL");
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