linux_dsm_epyc7002/drivers/clk/tegra
Linus Torvalds dc2535be1f We have a fairly balanced mix of clk driver updates and clk framework
updates this time around. It's the usual pile of new drivers for new
 hardware out there and the normal small fixes and updates, but then we
 have some core framework changes too.
 
 In the core framework, we introduce support for a clk_get_optional() API
 to get clks that may not always be populated and a way to devm manage clkdev
 lookups registered by provider drivers. We also do some refactoring to simplify
 the interface between clkdev and the common clk framework so we can reuse the DT
 parsing and clk_get() path in provider drivers in the future. This work will
 continue in the next few cycles while we convert how providers specify clk
 parents.
 
 On the driver side, the biggest part of the dirstat is the Amlogic clk driver
 that got support for the G12A SoC. It dominates with almost half the overall
 diff, while the second largest part of the diff is in the i.MX clk driver
 that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor
 and Qualcomm drivers rounding out the big part of the dirstat because they both
 got new hardware support for SoCs. The rest is just various updates and non-critical
 fixes for existing drivers.
 
 Core:
  - Convert a few clk bindings to JSON schema format
  - Add a {devm_}clk_get_optional() API
  - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
  - Start rewriting clk parent registration and supporting device links
    by moving around code that supports clk_get() and DT parsing of the
    'clocks' property
 
 New Drivers:
  - Add Qualcomm MSM8998 RPM managed clks
  - IPA clk support on Qualcomm RPMh clk controllers
  - Actions Semi S500 SoC clk support
  - Support for fixed rate clks populated from an MMIO register
  - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
  - Add TMU (timer) clocks on Renesas RZ/G2E
  - Add Amlogic G12A Always-On Clock Controller
  - Add 32k clock generation for Amlogic AXG
  - Add support for the Mali GPU clocks on Amlogic Meson8
  - Add Amlogic G12A EE clock controller driver
  - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
  - Add i.MX8MM SoC clk driver support
 
 Removed Drivers:
  - Remove clps711x driver as the board support is gone
 
 Updates:
  - 3rd ECO fix for Mediatek MT2712 SoCs
  - Updates for Qualcomm MSM8998 GCC clks
  - Random static analysis fixes for clk drivers
  - Support for sleeping gpios in the clk-gpio type
  - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
  - Split LCDC into two clks on the Marvell MMP2 SoC
  - Various DT of_node refcount fixes
  - Get rid of CLK_IS_BASIC from TI code (yay!)
  - TI Autoidle clk support
  - Fix Amlogic Meson8 APB clock ID name
  - Claim input clocks through DT for Amlogic AXG and GXBB
  - Correct the DU (display unit) parent clock on Renesas RZ/G2E
  - Exynos5433 IMEM CMU crypto clk support (SlimSS)
  - Fix for the PLL-MIPI on the Allwinner A23
  - Fix Rockchip rk3328 PLL rate calculation
  - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
  - i.MX SCU clk driver clk_set_parent() and cpufreq support
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlyIK9URHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUtIA//SRHcUJBuF7bgLs0GWDL/C0WwQf90bgLn
 83jMUX9MCIS+/RBEUi/Xf9psGVaW3YPEAiRcYUeI1YIZhCrdZHp2YGClKOpXaXth
 vgM7Je+6Say+7ru6J9eHqhbEgx2e+HqT4shxK5I5J0SqMFgdugim4pthk+Lr/WL0
 bMdNHTERZUFrIId10RxuCH7D72nhkwiRkwNDfWjASKoH3spXLKC1vl/wbS5QDE1O
 eXA9OwkonSyrBKX7zMeQiks6f7HWoJO7ei05Twv4CD9UEeS17KmB6mkbmT3GPAuq
 dWbLOnt7I80fMnthKLIR0IWtJuCvPv3jXgP+Fin+e4wutNCnuduHIVc2XeQYmDaX
 rbo/20q4DarL2AaakuowXA7UJ75zYfxPkwgpwcYZ/QW9yzT6QMfynAYekjJGTdt3
 6VootYAwYIsh1VMGZIQLs23AaNYayDy0QWx/prxnEi95lK/+zjqVySPYC/rWe7XQ
 rUrO6YY0YxRdf5uVHneIfIJGs5F/Q8DgdLXp4tf2Ud2YF1bZ0UQOUKehxwM0rxRX
 F9P6iP6mHUuUPMa9rDlwSmgQXDdqH7E5IbXdSPjEFBogBfmhJfVKAo1EyaZgUytZ
 Y42qG/P3fGGfegfWTRAoaDRJn/+HfEmtREdgQ8JO14xlZwRDb/M43IEiQP4zGwlc
 f/OuWu3O9xA=
 =D4Bv
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk subsystem updates from Stephen Boyd:
 "We have a fairly balanced mix of clk driver updates and clk framework
  updates this time around. It's the usual pile of new drivers for new
  hardware out there and the normal small fixes and updates, but then we
  have some core framework changes too.

  In the core framework, we introduce support for a clk_get_optional()
  API to get clks that may not always be populated and a way to devm
  manage clkdev lookups registered by provider drivers. We also do some
  refactoring to simplify the interface between clkdev and the common
  clk framework so we can reuse the DT parsing and clk_get() path in
  provider drivers in the future. This work will continue in the next
  few cycles while we convert how providers specify clk parents.

  On the driver side, the biggest part of the dirstat is the Amlogic clk
  driver that got support for the G12A SoC. It dominates with almost
  half the overall diff, while the second largest part of the diff is in
  the i.MX clk driver that gained support for imx8mm SoCs. After that,
  we have the Actions Semiconductor and Qualcomm drivers rounding out
  the big part of the dirstat because they both got new hardware support
  for SoCs. The rest is just various updates and non-critical fixes for
  existing drivers.

  Core:
   - Convert a few clk bindings to JSON schema format
   - Add a {devm_}clk_get_optional() API
   - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
   - Start rewriting clk parent registration and supporting device links
     by moving around code that supports clk_get() and DT parsing of the
     'clocks' property

  New Drivers:
   - Add Qualcomm MSM8998 RPM managed clks
   - IPA clk support on Qualcomm RPMh clk controllers
   - Actions Semi S500 SoC clk support
   - Support for fixed rate clks populated from an MMIO register
   - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
   - Add TMU (timer) clocks on Renesas RZ/G2E
   - Add Amlogic G12A Always-On Clock Controller
   - Add 32k clock generation for Amlogic AXG
   - Add support for the Mali GPU clocks on Amlogic Meson8
   - Add Amlogic G12A EE clock controller driver
   - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
   - Add i.MX8MM SoC clk driver support

  Removed Drivers:
   - Remove clps711x driver as the board support is gone

  Updates:
   - 3rd ECO fix for Mediatek MT2712 SoCs
   - Updates for Qualcomm MSM8998 GCC clks
   - Random static analysis fixes for clk drivers
   - Support for sleeping gpios in the clk-gpio type
   - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
   - Split LCDC into two clks on the Marvell MMP2 SoC
   - Various DT of_node refcount fixes
   - Get rid of CLK_IS_BASIC from TI code (yay!)
   - TI Autoidle clk support
   - Fix Amlogic Meson8 APB clock ID name
   - Claim input clocks through DT for Amlogic AXG and GXBB
   - Correct the DU (display unit) parent clock on Renesas RZ/G2E
   - Exynos5433 IMEM CMU crypto clk support (SlimSS)
   - Fix for the PLL-MIPI on the Allwinner A23
   - Fix Rockchip rk3328 PLL rate calculation
   - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
   - i.MX SCU clk driver clk_set_parent() and cpufreq support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
  dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
  clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT
  clk: fixup default index for of_clk_get_by_name()
  clk: Move of_clk_*() APIs into clk.c from clkdev.c
  clk: Inform the core about consumer devices
  clk: Introduce of_clk_get_hw_from_clkspec()
  clk: core: clarify the check for runtime PM
  clk: Combine __clk_get() and __clk_create_clk()
  clk: imx8mq: add GPIO clocks to clock tree
  clk: mediatek: correct cpu clock name for MT8173 SoC
  clk: imx: Refactor entire sccg pll clk
  clk: imx: scu: add cpu frequency scaling support
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
  clk: ingenic: Remove set but not used variable 'enable'
  clk: at91: programmable: remove unneeded register read
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2
  ...
2019-03-14 08:46:17 -07:00
..
clk-audio-sync.c clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
clk-bpmp.c clk: tegra: bpmp: Don't crash when a clock fails to register 2018-07-08 16:56:24 -07:00
clk-dfll.c We have a fairly balanced mix of clk driver updates and clk framework 2019-03-14 08:46:17 -07:00
clk-dfll.h clk: tegra: dfll: CVB calculation alignment with the regulator 2019-02-06 14:28:41 +01:00
clk-divider.c Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next 2018-08-14 22:58:53 -07:00
clk-emc.c clk: tegra: emc: Avoid out-of-bounds bug 2018-07-08 17:10:19 -07:00
clk-id.h clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks 2018-07-25 14:26:22 -07:00
clk-periph-fixed.c clk: tegra: Add fixed factor peripheral clock type 2016-04-28 12:41:47 +02:00
clk-periph-gate.c clk: tegra: Fix disable unused for clocks sharing enable bit 2017-03-20 14:13:52 +01:00
clk-periph.c clk: tegra: Add peripheral clock registration helper 2017-10-19 16:38:40 +02:00
clk-pll-out.c clk: tegra: Properly include clk.h 2015-07-20 11:11:17 -07:00
clk-pll.c clk: tegra: Return the exact clock rate from clk_round_rate 2018-12-14 13:32:55 -08:00
clk-sdmmc-mux.c clk: tegra: Add sdmmc mux divider clock 2018-07-25 13:45:09 -07:00
clk-super.c clk: tegra: Add super clock mux/divider 2017-03-20 14:07:33 +01:00
clk-tegra20.c clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC 2018-11-08 12:47:18 +01:00
clk-tegra30.c clk: tegra30: Use Tegra CPU powergate helper function 2018-12-14 13:32:55 -08:00
clk-tegra114.c clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
clk-tegra124-dfll-fcpu.c clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static 2019-02-18 11:16:22 +01:00
clk-tegra124.c clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
clk-tegra210.c clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
clk-tegra-audio.c clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
clk-tegra-fixed.c clk: tegra: Remove trailing blank line 2016-04-28 12:41:45 +02:00
clk-tegra-periph.c clk: tegra: get rid of duplicate defines 2018-12-14 13:32:54 -08:00
clk-tegra-pmc.c clk: tegra: Propagate clk_out_x rate to parent 2017-04-04 16:00:28 +02:00
clk-tegra-super-gen4.c clk: tegra: Mark HCLK, SCLK and EMC as critical 2018-03-12 13:58:58 +01:00
clk-utils.c clk: tegra: Refactor fractional divider calculation 2018-07-25 13:43:34 -07:00
clk.c treewide: kzalloc() -> kcalloc() 2018-06-12 16:19:22 -07:00
clk.h clk: tegra: Fix maximum audio sync clock for Tegra124/210 2018-12-14 13:32:55 -08:00
cvb.c clk: tegra: dfll: CVB calculation alignment with the regulator 2019-02-06 14:28:41 +01:00
cvb.h clk: tegra: dfll: add CVB tables for Tegra210 2019-02-06 14:29:23 +01:00
Kconfig clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 2019-02-06 14:29:37 +01:00
Makefile clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 2019-02-06 14:29:37 +01:00