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67f96ff7c8
In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power domain. This is similar to the other hardware modules and their power domains. However there is one thing specific to G3D clocks hierarchy. Unlike other hardware modules, the G3D clocks hierarchy doesn't have any gate clock between the TOP part of the hierarchy and the part located in the power domain and some SoC internal busses are sourced directly from the TOP muxes. The consequence of this design if the fact that the TOP part of the hierarchy has to be enabled permanently to ensure proper operation of the SoC power related components (G3D power domain and Exynos Power Management Unit for system suspend/resume). This patch adds an explicit call to clk_prepare_enable() on the last MUX in the TOP part of G3D clock hierarchy to keep it enabled permanently to ensure that the internal busses get their clock regardless of the main G3D clock enablement status. This fixes following imprecise abort issue observed on Odroid XU3/XU4 after enabling Panfrost driver by commit |
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| .. | ||
| clk-cpu.c | ||
| clk-cpu.h | ||
| clk-exynos4.c | ||
| clk-exynos5-subcmu.c | ||
| clk-exynos5-subcmu.h | ||
| clk-exynos7.c | ||
| clk-exynos3250.c | ||
| clk-exynos4412-isp.c | ||
| clk-exynos5250.c | ||
| clk-exynos5260.c | ||
| clk-exynos5260.h | ||
| clk-exynos5410.c | ||
| clk-exynos5420.c | ||
| clk-exynos5433.c | ||
| clk-exynos-audss.c | ||
| clk-exynos-clkout.c | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-s3c64xx.c | ||
| clk-s3c2410-dclk.c | ||
| clk-s3c2410.c | ||
| clk-s3c2412.c | ||
| clk-s3c2443.c | ||
| clk-s5pv210-audss.c | ||
| clk-s5pv210.c | ||
| clk.c | ||
| clk.h | ||
| Kconfig | ||
| Makefile | ||