mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 01:45:20 +07:00
e52a632195
The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most other IP blocks on this SoC the register values are only 16-bit wide. Like other IP blocks on this SoC the register values are in big endian. The PHY embeds a PLL which can be configured in various modes. Only the 36MHz mode is supported for now, the other modes can be implemented when there's a board which actually needs them. OpenWrt uses the out-of-tree vendor driver and all supported boards there only need the 36MHz mode. There are two input clocks: - the "pdi" clock enables the register access - the "phy" clock is the clock input and enables the internal PLL There are two reset lines: - "phy" resets the PHY itself - the "pcie" reset line is shared between the PHY and the PCIe controller While the VRX200 SoC has only one PCIe controller and PHY the ARX300 uses two identical PCIe controllers and PHYs which are compatible with the PCIe controller and PHY on VRX200. Add a driver for this PHY so PCIe support can be enabled on these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
22 lines
603 B
Plaintext
22 lines
603 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# Phy drivers for Lantiq / Intel platforms
|
|
#
|
|
config PHY_LANTIQ_VRX200_PCIE
|
|
tristate "Lantiq VRX200/ARX300 PCIe PHY"
|
|
depends on SOC_TYPE_XWAY || COMPILE_TEST
|
|
depends on OF && HAS_IOMEM
|
|
select GENERIC_PHY
|
|
select REGMAP_MMIO
|
|
help
|
|
Support for the PCIe PHY(s) on the Lantiq / Intel VRX200 and ARX300
|
|
family SoCs.
|
|
If unsure, say N.
|
|
|
|
config PHY_LANTIQ_RCU_USB2
|
|
tristate "Lantiq XWAY SoC RCU based USB PHY"
|
|
depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)
|
|
select GENERIC_PHY
|
|
help
|
|
Support for the USB PHY(s) on the Lantiq / Intel XWAY family SoCs.
|