mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 04:46:32 +07:00
53e155f2bb
+ usual progress on cleanups
+ dsi vs EPROBE_DEFER fixes
+ msm8998 (snapdragon 835 support)
+ a540 gpu support (mesa support already landed)
+ dsi, dsi-phy support
+ mdp5 and dpu interconnect (bus/memory scaling) support
+ initial prep work for per-context pagetables (at least the parts that
don't have external dependencies like iommu/arm-smmu)
There is one more patch for fixing DSI cmd mode panels (part of a set of
patches to get things working on nexus5), but it would be conflicty with
1cff7440a8 in drm-next without rebasing or back-merge,
and since it doesn't conflict with anything in msm-next, I think it best
if Sean merges that through drm-mix-fixes instead.
(In other news, I've been making some progress w/ getting efifb working
properly on sdm850 laptop without horrible hacks, and drm/msm + clk stuff
not totally falling over when bootloader enables display and things are
already running when driver probes.. but not quite ready yet, hopefully
we can post some of that for 5.4.. should help for both the sdm835 and
sdm850 laptops.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsj3N4XzDLSDoa+4RHZ9wXObYmhcep0M3LjnRg48BeLvg@mail.gmail.com
222 lines
6.0 KiB
C
222 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include "dsi_cfg.h"
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static const char * const dsi_v2_bus_clk_names[] = {
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"core_mmss", "iface", "bus",
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};
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static const struct msm_dsi_config apq8064_dsi_cfg = {
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.io_offset = 0,
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.reg_cfg = {
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.num = 3,
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.regs = {
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{"vdda", 100000, 100}, /* 1.2 V */
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{"avdd", 10000, 100}, /* 3.0 V */
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{"vddio", 100000, 100}, /* 1.8 V */
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},
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},
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.bus_clk_names = dsi_v2_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
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.io_start = { 0x4700000, 0x5800000 },
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.num_dsi = 2,
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};
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static const char * const dsi_6g_bus_clk_names[] = {
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"mdp_core", "iface", "bus", "core_mmss",
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};
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static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 4,
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.regs = {
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{"gdsc", -1, -1},
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{"vdd", 150000, 100}, /* 3.0 V */
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{"vdda", 100000, 100}, /* 1.2 V */
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{"vddio", 100000, 100}, /* 1.8 V */
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},
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},
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.bus_clk_names = dsi_6g_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
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.io_start = { 0xfd922800, 0xfd922b00 },
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.num_dsi = 2,
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};
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static const char * const dsi_8916_bus_clk_names[] = {
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"mdp_core", "iface", "bus",
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};
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static const struct msm_dsi_config msm8916_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 3,
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.regs = {
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{"gdsc", -1, -1},
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{"vdda", 100000, 100}, /* 1.2 V */
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{"vddio", 100000, 100}, /* 1.8 V */
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},
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},
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.bus_clk_names = dsi_8916_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
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.io_start = { 0x1a98000 },
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.num_dsi = 1,
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};
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static const struct msm_dsi_config msm8994_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 7,
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.regs = {
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{"gdsc", -1, -1},
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{"vdda", 100000, 100}, /* 1.25 V */
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{"vddio", 100000, 100}, /* 1.8 V */
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{"vcca", 10000, 100}, /* 1.0 V */
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{"vdd", 100000, 100}, /* 1.8 V */
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{"lab_reg", -1, -1},
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{"ibb_reg", -1, -1},
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},
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},
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.bus_clk_names = dsi_6g_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
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.io_start = { 0xfd998000, 0xfd9a0000 },
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.num_dsi = 2,
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};
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/*
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* TODO: core_mmss_clk fails to enable for some reason, but things work fine
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* without it too. Figure out why it doesn't enable and uncomment below
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*/
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static const char * const dsi_8996_bus_clk_names[] = {
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"mdp_core", "iface", "bus", /* "core_mmss", */
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};
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static const struct msm_dsi_config msm8996_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 2,
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.regs = {
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{"vdda", 18160, 1 }, /* 1.25 V */
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{"vcca", 17000, 32 }, /* 0.925 V */
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{"vddio", 100000, 100 },/* 1.8 V */
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},
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},
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.bus_clk_names = dsi_8996_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
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.io_start = { 0x994000, 0x996000 },
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.num_dsi = 2,
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};
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static const char * const dsi_msm8998_bus_clk_names[] = {
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"iface", "bus", "core",
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};
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static const struct msm_dsi_config msm8998_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 2,
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.regs = {
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{"vdd", 367000, 16 }, /* 0.9 V */
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{"vdda", 62800, 2 }, /* 1.2 V */
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},
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},
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.bus_clk_names = dsi_msm8998_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
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.io_start = { 0xc994000, 0xc996000 },
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.num_dsi = 2,
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};
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static const char * const dsi_sdm845_bus_clk_names[] = {
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"iface", "bus",
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};
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static const struct msm_dsi_config sdm845_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 1,
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.regs = {
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{"vdda", 21800, 4 }, /* 1.2 V */
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},
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},
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.bus_clk_names = dsi_sdm845_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
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.io_start = { 0xae94000, 0xae96000 },
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.num_dsi = 2,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_v2,
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.link_clk_disable = dsi_link_clk_disable_v2,
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.clk_init_ver = dsi_clk_init_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_v2,
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.tx_buf_get = dsi_tx_buf_get_v2,
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.tx_buf_put = NULL,
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.dma_base_get = dsi_dma_base_get_v2,
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.calc_clk_rate = dsi_calc_clk_rate_v2,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = NULL,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = dsi_clk_init_6g_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
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{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
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&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
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&msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
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&msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
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&msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
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&msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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};
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const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
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{
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const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
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int i;
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for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
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if ((dsi_cfg_handlers[i].major == major) &&
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(dsi_cfg_handlers[i].minor == minor)) {
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cfg_hnd = &dsi_cfg_handlers[i];
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break;
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}
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}
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return cfg_hnd;
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}
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