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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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387720c938
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
429 lines
11 KiB
Plaintext
429 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Erin.Lo <erin.lo@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include "skeleton64.dtsi"
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#include "mt2701-pinfunc.h"
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/ {
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compatible = "mediatek,mt2701";
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal 0>;
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sustainable-power = <1000>;
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trips {
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threshold: trip-point@0 {
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temperature = <68000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit@0 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2701-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt2701-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt2701-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt2701-scpsys", "syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt2701-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt2701-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2701-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt2701-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <0>;
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compatible = "mediatek,mt2701-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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status = "disabled";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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status = "disabled";
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};
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spi1: spi@11016000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11016000 0 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI1_SEL>,
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<&pericfg CLK_PERI_SPI1>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi2: spi@11017000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11017000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI2_SEL>,
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<&pericfg CLK_PERI_SPI2>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt2701-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt2701-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt2701-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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};
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt2701-hifsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt2701-ethsys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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bdpsys: syscon@1c000000 {
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compatible = "mediatek,mt2701-bdpsys", "syscon";
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reg = <0 0x1c000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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