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d400f209b4
The existing Tegra USB bindings have a few issues: 1) Many properties are documented as being part of the EHCI controller node, yet they apply more to the PHY device. They should be moved. 2) Some registers in PHY1 are shared with PHY3, and hence PHY3 needs a reg entry to point at PHY1's register space. We can't assume the PHY1 driver is present, so the PHY3 driver will directly access those registers. 3) The list of clocks required by the PHY was missing some required entries. 4) UTMI PHY Timing parameters are added 5) VBUS control is now specified using a regulator rather than a plain GPIO 6) Added nvidia,is-wired property to indicate whether the device is hard wired on the board, or pluggable. This patch fixes the binding definition to resolve these issues. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
16 lines
614 B
Plaintext
16 lines
614 B
Plaintext
Tegra SOC USB controllers
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The device node for a USB controller that is part of a Tegra
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SOC is as described in the document "Open Firmware Recommended
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Practice : Universal Serial Bus" with the following modifications
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and additions :
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Required properties :
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- compatible : Should be "nvidia,tegra20-ehci".
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- nvidia,phy : phandle of the PHY that the controller is connected to.
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- clocks : Contains a single entry which defines the USB controller's clock.
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Optional properties:
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- nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
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USB ports, which need reset twice due to hardware issues.
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