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16a9dea110
DCN requires floating point support to operate. Add the appropriate x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN. Note that the current DC20 code doesn't contain all required FPU wrappers on x86 or POWER, so this patch is insufficient to fully enable DC20 on POWER. v2: s/X86_64/X86/g to retain previous behavior. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
37 lines
874 B
Plaintext
37 lines
874 B
Plaintext
# SPDX-License-Identifier: MIT
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menu "Display Engine Configuration"
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depends on DRM && DRM_AMDGPU
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config DRM_AMD_DC
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bool "AMD DC - Enable new display engine"
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default y
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select SND_HDA_COMPONENT if SND_HDA_CORE
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select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
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help
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Choose this option if you want to use the new display engine
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support for AMDGPU. This adds required support for Vega and
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Raven ASICs.
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config DRM_AMD_DC_DCN
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def_bool n
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help
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Raven, Navi and Renoir family support for display engine
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config DRM_AMD_DC_HDCP
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bool "Enable HDCP support in DC"
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depends on DRM_AMD_DC
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help
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Choose this option
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if you want to support
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HDCP authentication
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config DEBUG_KERNEL_DC
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bool "Enable kgdb break in DC"
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depends on DRM_AMD_DC
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help
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Choose this option
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if you want to hit
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kdgb_break in assert.
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endmenu
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