mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 17:06:41 +07:00
9137bb27e6
Add the PR_SPEC_INDIRECT_BRANCH option for the PR_GET_SPECULATION_CTRL and PR_SET_SPECULATION_CTRL prctls to allow fine grained per task control of indirect branch speculation via STIBP and IBPB. Invocations: Check indirect branch speculation status with - prctl(PR_GET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, 0, 0, 0); Enable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_ENABLE, 0, 0); Disable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_DISABLE, 0, 0); Force disable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_FORCE_DISABLE, 0, 0); See Documentation/userspace-api/spec_ctrl.rst. Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Andi Kleen <ak@linux.intel.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Casey Schaufler <casey.schaufler@intel.com> Cc: Asit Mallick <asit.k.mallick@intel.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Jon Masters <jcm@redhat.com> Cc: Waiman Long <longman9394@gmail.com> Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Dave Stewart <david.c.stewart@intel.com> Cc: Kees Cook <keescook@chromium.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.866780996@linutronix.de
859 lines
21 KiB
C
859 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/prctl.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/sched/idle.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/random.h>
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#include <linux/user-return-notifier.h>
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#include <linux/dmi.h>
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#include <linux/utsname.h>
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#include <linux/stackprotector.h>
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#include <linux/cpuidle.h>
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#include <trace/events/power.h>
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#include <linux/hw_breakpoint.h>
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#include <asm/cpu.h>
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#include <asm/apic.h>
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#include <asm/syscalls.h>
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#include <linux/uaccess.h>
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#include <asm/mwait.h>
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#include <asm/fpu/internal.h>
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#include <asm/debugreg.h>
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#include <asm/nmi.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/vm86.h>
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#include <asm/switch_to.h>
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#include <asm/desc.h>
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#include <asm/prctl.h>
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#include <asm/spec-ctrl.h>
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#include "process.h"
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/*
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* per-CPU TSS segments. Threads are completely 'soft' on Linux,
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* no more per-task TSS's. The TSS size is kept cacheline-aligned
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* so they are allowed to end up in the .data..cacheline_aligned
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
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.x86_tss = {
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/*
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* .sp0 is only used when entering ring 0 from a lower
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* privilege level. Since the init task never runs anything
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* but ring 0 code, there is no need for a valid value here.
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* Poison it.
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*/
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.sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
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/*
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* .sp1 is cpu_current_top_of_stack. The init task never
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* runs user code, but cpu_current_top_of_stack should still
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* be well defined before the first context switch.
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*/
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.sp1 = TOP_OF_INIT_STACK,
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#ifdef CONFIG_X86_32
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.ss0 = __KERNEL_DS,
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.ss1 = __KERNEL_CS,
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
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#endif
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},
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#ifdef CONFIG_X86_32
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/*
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* Note that the .io_bitmap member must be extra-big. This is because
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* the CPU will access an additional byte beyond the end of the IO
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* permission bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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.io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
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#endif
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};
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EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
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DEFINE_PER_CPU(bool, __tss_limit_invalid);
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EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
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/*
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* this gets called so that we can store lazy state into memory and copy the
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* current task into the new thread.
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*/
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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memcpy(dst, src, arch_task_struct_size);
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#ifdef CONFIG_VM86
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dst->thread.vm86 = NULL;
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#endif
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return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
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}
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/*
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* Free current thread data structures etc..
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*/
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void exit_thread(struct task_struct *tsk)
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{
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struct thread_struct *t = &tsk->thread;
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unsigned long *bp = t->io_bitmap_ptr;
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struct fpu *fpu = &t->fpu;
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if (bp) {
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struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
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t->io_bitmap_ptr = NULL;
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clear_thread_flag(TIF_IO_BITMAP);
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/*
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* Careful, clear this in the TSS too:
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*/
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memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
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t->io_bitmap_max = 0;
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put_cpu();
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kfree(bp);
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}
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free_vm86(t);
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fpu__drop(fpu);
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}
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void flush_thread(void)
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{
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struct task_struct *tsk = current;
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flush_ptrace_hw_breakpoint(tsk);
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memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
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fpu__clear(&tsk->thread.fpu);
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}
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void disable_TSC(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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cr4_set_bits(X86_CR4_TSD);
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preempt_enable();
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}
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static void enable_TSC(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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cr4_clear_bits(X86_CR4_TSD);
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preempt_enable();
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}
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int get_tsc_mode(unsigned long adr)
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{
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unsigned int val;
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if (test_thread_flag(TIF_NOTSC))
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val = PR_TSC_SIGSEGV;
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else
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val = PR_TSC_ENABLE;
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return put_user(val, (unsigned int __user *)adr);
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}
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int set_tsc_mode(unsigned int val)
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{
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if (val == PR_TSC_SIGSEGV)
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disable_TSC();
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else if (val == PR_TSC_ENABLE)
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enable_TSC();
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else
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return -EINVAL;
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return 0;
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}
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DEFINE_PER_CPU(u64, msr_misc_features_shadow);
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static void set_cpuid_faulting(bool on)
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{
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u64 msrval;
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msrval = this_cpu_read(msr_misc_features_shadow);
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msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
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msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
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this_cpu_write(msr_misc_features_shadow, msrval);
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wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
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}
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static void disable_cpuid(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOCPUID)) {
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOCPUID in the current running context.
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*/
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set_cpuid_faulting(true);
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}
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preempt_enable();
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}
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static void enable_cpuid(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOCPUID)) {
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOCPUID in the current running context.
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*/
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set_cpuid_faulting(false);
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}
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preempt_enable();
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}
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static int get_cpuid_mode(void)
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{
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return !test_thread_flag(TIF_NOCPUID);
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}
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static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
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{
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if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
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return -ENODEV;
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if (cpuid_enabled)
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enable_cpuid();
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else
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disable_cpuid();
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return 0;
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}
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/*
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* Called immediately after a successful exec.
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*/
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void arch_setup_new_exec(void)
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{
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/* If cpuid was previously disabled for this task, re-enable it. */
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if (test_thread_flag(TIF_NOCPUID))
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enable_cpuid();
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}
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static inline void switch_to_bitmap(struct thread_struct *prev,
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struct thread_struct *next,
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unsigned long tifp, unsigned long tifn)
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{
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struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
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if (tifn & _TIF_IO_BITMAP) {
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/*
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* Copy the relevant range of the IO bitmap.
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* Normally this is 128 bytes or less:
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*/
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memcpy(tss->io_bitmap, next->io_bitmap_ptr,
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max(prev->io_bitmap_max, next->io_bitmap_max));
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/*
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* Make sure that the TSS limit is correct for the CPU
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* to notice the IO bitmap.
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*/
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refresh_tss_limit();
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} else if (tifp & _TIF_IO_BITMAP) {
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/*
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* Clear any possible leftover bits:
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*/
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memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
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}
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}
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#ifdef CONFIG_SMP
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struct ssb_state {
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struct ssb_state *shared_state;
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raw_spinlock_t lock;
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unsigned int disable_state;
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unsigned long local_state;
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};
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#define LSTATE_SSB 0
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static DEFINE_PER_CPU(struct ssb_state, ssb_state);
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void speculative_store_bypass_ht_init(void)
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{
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struct ssb_state *st = this_cpu_ptr(&ssb_state);
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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st->local_state = 0;
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/*
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* Shared state setup happens once on the first bringup
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* of the CPU. It's not destroyed on CPU hotunplug.
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*/
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if (st->shared_state)
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return;
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raw_spin_lock_init(&st->lock);
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/*
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* Go over HT siblings and check whether one of them has set up the
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* shared state pointer already.
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*/
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for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
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if (cpu == this_cpu)
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continue;
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if (!per_cpu(ssb_state, cpu).shared_state)
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continue;
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/* Link it to the state of the sibling: */
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st->shared_state = per_cpu(ssb_state, cpu).shared_state;
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return;
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}
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/*
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* First HT sibling to come up on the core. Link shared state of
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* the first HT sibling to itself. The siblings on the same core
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* which come up later will see the shared state pointer and link
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* themself to the state of this CPU.
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*/
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st->shared_state = st;
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}
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/*
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* Logic is: First HT sibling enables SSBD for both siblings in the core
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* and last sibling to disable it, disables it for the whole core. This how
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* MSR_SPEC_CTRL works in "hardware":
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*
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* CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
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*/
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static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
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{
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struct ssb_state *st = this_cpu_ptr(&ssb_state);
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u64 msr = x86_amd_ls_cfg_base;
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if (!static_cpu_has(X86_FEATURE_ZEN)) {
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msr |= ssbd_tif_to_amd_ls_cfg(tifn);
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wrmsrl(MSR_AMD64_LS_CFG, msr);
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return;
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}
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if (tifn & _TIF_SSBD) {
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/*
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* Since this can race with prctl(), block reentry on the
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* same CPU.
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*/
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if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
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return;
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msr |= x86_amd_ls_cfg_ssbd_mask;
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raw_spin_lock(&st->shared_state->lock);
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/* First sibling enables SSBD: */
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if (!st->shared_state->disable_state)
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wrmsrl(MSR_AMD64_LS_CFG, msr);
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st->shared_state->disable_state++;
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raw_spin_unlock(&st->shared_state->lock);
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} else {
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if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
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return;
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raw_spin_lock(&st->shared_state->lock);
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st->shared_state->disable_state--;
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if (!st->shared_state->disable_state)
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wrmsrl(MSR_AMD64_LS_CFG, msr);
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raw_spin_unlock(&st->shared_state->lock);
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}
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}
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#else
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static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
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{
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u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
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wrmsrl(MSR_AMD64_LS_CFG, msr);
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}
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#endif
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static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
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{
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/*
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* SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
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* so ssbd_tif_to_spec_ctrl() just works.
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*/
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wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
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}
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/*
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* Update the MSRs managing speculation control, during context switch.
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*
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* tifp: Previous task's thread flags
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* tifn: Next task's thread flags
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*/
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static __always_inline void __speculation_ctrl_update(unsigned long tifp,
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unsigned long tifn)
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{
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unsigned long tif_diff = tifp ^ tifn;
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u64 msr = x86_spec_ctrl_base;
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bool updmsr = false;
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/*
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* If TIF_SSBD is different, select the proper mitigation
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* method. Note that if SSBD mitigation is disabled or permanentely
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* enabled this branch can't be taken because nothing can set
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* TIF_SSBD.
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*/
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if (tif_diff & _TIF_SSBD) {
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if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
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amd_set_ssb_virt_state(tifn);
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} else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
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amd_set_core_ssb_state(tifn);
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} else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
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static_cpu_has(X86_FEATURE_AMD_SSBD)) {
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msr |= ssbd_tif_to_spec_ctrl(tifn);
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updmsr = true;
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}
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}
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/*
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* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled,
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* otherwise avoid the MSR write.
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*/
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if (IS_ENABLED(CONFIG_SMP) &&
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static_branch_unlikely(&switch_to_cond_stibp)) {
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updmsr |= !!(tif_diff & _TIF_SPEC_IB);
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msr |= stibp_tif_to_spec_ctrl(tifn);
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}
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if (updmsr)
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wrmsrl(MSR_IA32_SPEC_CTRL, msr);
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}
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static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
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{
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if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
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if (task_spec_ssb_disable(tsk))
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set_tsk_thread_flag(tsk, TIF_SSBD);
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else
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clear_tsk_thread_flag(tsk, TIF_SSBD);
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if (task_spec_ib_disable(tsk))
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set_tsk_thread_flag(tsk, TIF_SPEC_IB);
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else
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clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
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}
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/* Return the updated threadinfo flags*/
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return task_thread_info(tsk)->flags;
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}
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void speculation_ctrl_update(unsigned long tif)
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{
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/* Forced update. Make sure all relevant TIF flags are different */
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preempt_disable();
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__speculation_ctrl_update(~tif, tif);
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preempt_enable();
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}
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/* Called from seccomp/prctl update */
|
|
void speculation_ctrl_update_current(void)
|
|
{
|
|
preempt_disable();
|
|
speculation_ctrl_update(speculation_ctrl_update_tif(current));
|
|
preempt_enable();
|
|
}
|
|
|
|
void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
|
|
{
|
|
struct thread_struct *prev, *next;
|
|
unsigned long tifp, tifn;
|
|
|
|
prev = &prev_p->thread;
|
|
next = &next_p->thread;
|
|
|
|
tifn = READ_ONCE(task_thread_info(next_p)->flags);
|
|
tifp = READ_ONCE(task_thread_info(prev_p)->flags);
|
|
switch_to_bitmap(prev, next, tifp, tifn);
|
|
|
|
propagate_user_return_notify(prev_p, next_p);
|
|
|
|
if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
|
|
arch_has_block_step()) {
|
|
unsigned long debugctl, msk;
|
|
|
|
rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
|
|
debugctl &= ~DEBUGCTLMSR_BTF;
|
|
msk = tifn & _TIF_BLOCKSTEP;
|
|
debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
|
|
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
|
|
}
|
|
|
|
if ((tifp ^ tifn) & _TIF_NOTSC)
|
|
cr4_toggle_bits_irqsoff(X86_CR4_TSD);
|
|
|
|
if ((tifp ^ tifn) & _TIF_NOCPUID)
|
|
set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
|
|
|
|
if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
|
|
__speculation_ctrl_update(tifp, tifn);
|
|
} else {
|
|
speculation_ctrl_update_tif(prev_p);
|
|
tifn = speculation_ctrl_update_tif(next_p);
|
|
|
|
/* Enforce MSR update to ensure consistent state */
|
|
__speculation_ctrl_update(~tifn, tifn);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Idle related variables and functions
|
|
*/
|
|
unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
|
|
EXPORT_SYMBOL(boot_option_idle_override);
|
|
|
|
static void (*x86_idle)(void);
|
|
|
|
#ifndef CONFIG_SMP
|
|
static inline void play_dead(void)
|
|
{
|
|
BUG();
|
|
}
|
|
#endif
|
|
|
|
void arch_cpu_idle_enter(void)
|
|
{
|
|
tsc_verify_tsc_adjust(false);
|
|
local_touch_nmi();
|
|
}
|
|
|
|
void arch_cpu_idle_dead(void)
|
|
{
|
|
play_dead();
|
|
}
|
|
|
|
/*
|
|
* Called from the generic idle code.
|
|
*/
|
|
void arch_cpu_idle(void)
|
|
{
|
|
x86_idle();
|
|
}
|
|
|
|
/*
|
|
* We use this if we don't have any better idle routine..
|
|
*/
|
|
void __cpuidle default_idle(void)
|
|
{
|
|
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
|
safe_halt();
|
|
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
|
}
|
|
#ifdef CONFIG_APM_MODULE
|
|
EXPORT_SYMBOL(default_idle);
|
|
#endif
|
|
|
|
#ifdef CONFIG_XEN
|
|
bool xen_set_default_idle(void)
|
|
{
|
|
bool ret = !!x86_idle;
|
|
|
|
x86_idle = default_idle;
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
void stop_this_cpu(void *dummy)
|
|
{
|
|
local_irq_disable();
|
|
/*
|
|
* Remove this CPU:
|
|
*/
|
|
set_cpu_online(smp_processor_id(), false);
|
|
disable_local_APIC();
|
|
mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
|
|
|
|
/*
|
|
* Use wbinvd on processors that support SME. This provides support
|
|
* for performing a successful kexec when going from SME inactive
|
|
* to SME active (or vice-versa). The cache must be cleared so that
|
|
* if there are entries with the same physical address, both with and
|
|
* without the encryption bit, they don't race each other when flushed
|
|
* and potentially end up with the wrong entry being committed to
|
|
* memory.
|
|
*/
|
|
if (boot_cpu_has(X86_FEATURE_SME))
|
|
native_wbinvd();
|
|
for (;;) {
|
|
/*
|
|
* Use native_halt() so that memory contents don't change
|
|
* (stack usage and variables) after possibly issuing the
|
|
* native_wbinvd() above.
|
|
*/
|
|
native_halt();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
|
|
* states (local apic timer and TSC stop).
|
|
*/
|
|
static void amd_e400_idle(void)
|
|
{
|
|
/*
|
|
* We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
|
|
* gets set after static_cpu_has() places have been converted via
|
|
* alternatives.
|
|
*/
|
|
if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
|
|
default_idle();
|
|
return;
|
|
}
|
|
|
|
tick_broadcast_enter();
|
|
|
|
default_idle();
|
|
|
|
/*
|
|
* The switch back from broadcast mode needs to be called with
|
|
* interrupts disabled.
|
|
*/
|
|
local_irq_disable();
|
|
tick_broadcast_exit();
|
|
local_irq_enable();
|
|
}
|
|
|
|
/*
|
|
* Intel Core2 and older machines prefer MWAIT over HALT for C1.
|
|
* We can't rely on cpuidle installing MWAIT, because it will not load
|
|
* on systems that support only C1 -- so the boot default must be MWAIT.
|
|
*
|
|
* Some AMD machines are the opposite, they depend on using HALT.
|
|
*
|
|
* So for default C1, which is used during boot until cpuidle loads,
|
|
* use MWAIT-C1 on Intel HW that has it, else use HALT.
|
|
*/
|
|
static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
|
|
{
|
|
if (c->x86_vendor != X86_VENDOR_INTEL)
|
|
return 0;
|
|
|
|
if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
|
|
* with interrupts enabled and no flags, which is backwards compatible with the
|
|
* original MWAIT implementation.
|
|
*/
|
|
static __cpuidle void mwait_idle(void)
|
|
{
|
|
if (!current_set_polling_and_test()) {
|
|
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
|
if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
|
|
mb(); /* quirk */
|
|
clflush((void *)¤t_thread_info()->flags);
|
|
mb(); /* quirk */
|
|
}
|
|
|
|
__monitor((void *)¤t_thread_info()->flags, 0, 0);
|
|
if (!need_resched())
|
|
__sti_mwait(0, 0);
|
|
else
|
|
local_irq_enable();
|
|
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
|
} else {
|
|
local_irq_enable();
|
|
}
|
|
__current_clr_polling();
|
|
}
|
|
|
|
void select_idle_routine(const struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
|
|
pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
|
|
#endif
|
|
if (x86_idle || boot_option_idle_override == IDLE_POLL)
|
|
return;
|
|
|
|
if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
|
|
pr_info("using AMD E400 aware idle routine\n");
|
|
x86_idle = amd_e400_idle;
|
|
} else if (prefer_mwait_c1_over_halt(c)) {
|
|
pr_info("using mwait in idle threads\n");
|
|
x86_idle = mwait_idle;
|
|
} else
|
|
x86_idle = default_idle;
|
|
}
|
|
|
|
void amd_e400_c1e_apic_setup(void)
|
|
{
|
|
if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
|
|
pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
|
|
local_irq_disable();
|
|
tick_broadcast_force();
|
|
local_irq_enable();
|
|
}
|
|
}
|
|
|
|
void __init arch_post_acpi_subsys_init(void)
|
|
{
|
|
u32 lo, hi;
|
|
|
|
if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
|
|
return;
|
|
|
|
/*
|
|
* AMD E400 detection needs to happen after ACPI has been enabled. If
|
|
* the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
|
|
* MSR_K8_INT_PENDING_MSG.
|
|
*/
|
|
rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
|
|
if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
|
|
return;
|
|
|
|
boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
|
|
mark_tsc_unstable("TSC halt in AMD C1E");
|
|
pr_info("System has AMD C1E enabled\n");
|
|
}
|
|
|
|
static int __init idle_setup(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "poll")) {
|
|
pr_info("using polling idle threads\n");
|
|
boot_option_idle_override = IDLE_POLL;
|
|
cpu_idle_poll_ctrl(true);
|
|
} else if (!strcmp(str, "halt")) {
|
|
/*
|
|
* When the boot option of idle=halt is added, halt is
|
|
* forced to be used for CPU idle. In such case CPU C2/C3
|
|
* won't be used again.
|
|
* To continue to load the CPU idle driver, don't touch
|
|
* the boot_option_idle_override.
|
|
*/
|
|
x86_idle = default_idle;
|
|
boot_option_idle_override = IDLE_HALT;
|
|
} else if (!strcmp(str, "nomwait")) {
|
|
/*
|
|
* If the boot option of "idle=nomwait" is added,
|
|
* it means that mwait will be disabled for CPU C2/C3
|
|
* states. In such case it won't touch the variable
|
|
* of boot_option_idle_override.
|
|
*/
|
|
boot_option_idle_override = IDLE_NOMWAIT;
|
|
} else
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
early_param("idle", idle_setup);
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() % 8192;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
{
|
|
return randomize_page(mm->brk, 0x02000000);
|
|
}
|
|
|
|
/*
|
|
* Called from fs/proc with a reference on @p to find the function
|
|
* which called into schedule(). This needs to be done carefully
|
|
* because the task might wake up and we might look at a stack
|
|
* changing under us.
|
|
*/
|
|
unsigned long get_wchan(struct task_struct *p)
|
|
{
|
|
unsigned long start, bottom, top, sp, fp, ip, ret = 0;
|
|
int count = 0;
|
|
|
|
if (!p || p == current || p->state == TASK_RUNNING)
|
|
return 0;
|
|
|
|
if (!try_get_task_stack(p))
|
|
return 0;
|
|
|
|
start = (unsigned long)task_stack_page(p);
|
|
if (!start)
|
|
goto out;
|
|
|
|
/*
|
|
* Layout of the stack page:
|
|
*
|
|
* ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
|
|
* PADDING
|
|
* ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
|
|
* stack
|
|
* ----------- bottom = start
|
|
*
|
|
* The tasks stack pointer points at the location where the
|
|
* framepointer is stored. The data on the stack is:
|
|
* ... IP FP ... IP FP
|
|
*
|
|
* We need to read FP and IP, so we need to adjust the upper
|
|
* bound by another unsigned long.
|
|
*/
|
|
top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
|
|
top -= 2 * sizeof(unsigned long);
|
|
bottom = start;
|
|
|
|
sp = READ_ONCE(p->thread.sp);
|
|
if (sp < bottom || sp > top)
|
|
goto out;
|
|
|
|
fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
|
|
do {
|
|
if (fp < bottom || fp > top)
|
|
goto out;
|
|
ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
|
|
if (!in_sched_functions(ip)) {
|
|
ret = ip;
|
|
goto out;
|
|
}
|
|
fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
|
|
} while (count++ < 16 && p->state != TASK_RUNNING);
|
|
|
|
out:
|
|
put_task_stack(p);
|
|
return ret;
|
|
}
|
|
|
|
long do_arch_prctl_common(struct task_struct *task, int option,
|
|
unsigned long cpuid_enabled)
|
|
{
|
|
switch (option) {
|
|
case ARCH_GET_CPUID:
|
|
return get_cpuid_mode();
|
|
case ARCH_SET_CPUID:
|
|
return set_cpuid_mode(task, cpuid_enabled);
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|