mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
8897f3255c
LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache
Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:
- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.
- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.
- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
340 lines
9.8 KiB
Plaintext
340 lines
9.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for NXP Layerscape-1028A family SoC.
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*
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* Copyright 2018 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,ls1028a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x1>;
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enable-method = "psci";
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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idle-states {
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/*
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* PSCI node is not added default, U-boot will add missing
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* parts if it determines to use PSCI.
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*/
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entry-method = "arm,psci";
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CPU_PH20: cpu-ph20 {
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compatible = "arm,idle-state";
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idle-state-name = "PH20";
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arm,psci-suspend-param = <0x00010000>;
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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};
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};
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sysclk: clock-sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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reboot {
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compatible ="syscon-reboot";
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regmap = <&dcfg>;
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offset = <0xb0>;
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mask = <0x02>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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gic: interrupt-controller@6000000 {
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compatible= "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
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#interrupt-cells= <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>;
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its: gic-its@6020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ddr: memory-controller@1080000 {
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compatible = "fsl,qoriq-memory-controller";
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reg = <0x0 0x1080000 0x0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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};
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dcfg: syscon@1e00000 {
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compatible = "fsl,ls1028a-dcfg", "syscon";
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reg = <0x0 0x1e00000 0x0 0x10000>;
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big-endian;
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};
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scfg: syscon@1fc0000 {
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compatible = "fsl,ls1028a-scfg", "syscon";
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reg = <0x0 0x1fc0000 0x0 0x10000>;
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big-endian;
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};
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clockgen: clock-controller@1300000 {
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compatible = "fsl,ls1028a-clockgen";
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reg = <0x0 0x1300000 0x0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c4: i2c@2040000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2040000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c5: i2c@2050000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2050000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c6: i2c@2060000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2060000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c7: i2c@2070000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2070000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0500 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0600 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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gpio1: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2310000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2320000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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wdog0: watchdog@23c0000 {
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compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
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reg = <0x0 0x23c0000 0x0 0x10000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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big-endian;
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status = "disabled";
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1028a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>,
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<0x0 0x20140520 0x0 0x4>;
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reg-names = "ahci", "sata-ecc";
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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smmu: iommu@5000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x5000000 0 0x800000>;
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#global-interrupts = <8>;
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#iommu-cells = <1>;
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stream-match-mask = <0x7c00>;
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/* global secure fault */
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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/* combined secure interrupt */
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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/* global non-secure fault */
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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/* combined non-secure interrupt */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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/* performance counter interrupts 0-7 */
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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/* per context interrupt, 64 interrupts */
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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