linux_dsm_epyc7002/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
Bhaskar Upadhaya 8897f3255c arm64: dts: Add support for NXP LS1028A SoC
LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
 Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
  - Arranged as single clusters of two cores sharing a 1 MB L2 cache
  - Speed Up to 1.3 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 400 MHz
 32-bit DDR4 SDRAM memory controller with ECC
 Two PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Two high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1028A
  SoC family:

         - fsl-ls1028a.dtsi:
                 DTS-Include file for NXP LS1028A SoC.

         - fsl-ls1028a-qds.dts:
                 DTS file for NXP LS1028A QDS board.

         - fsl-ls1028a-rdb.dts:
                 DTS file for NXP LS1028A RDB board

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08 10:28:38 +08:00

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS1028A RDB Board.
*
* Copyright 2018 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "LS1028A RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0000000>;
};
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9847";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
current-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};