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LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache Features summary Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs - Arranged as single clusters of two cores sharing a 1 MB L2 cache - Speed Up to 1.3 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 400 MHz 32-bit DDR4 SDRAM memory controller with ECC Two PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Two high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1028A SoC family: - fsl-ls1028a.dtsi: DTS-Include file for NXP LS1028A SoC. - fsl-ls1028a-qds.dts: DTS file for NXP LS1028A QDS board. - fsl-ls1028a-rdb.dts: DTS file for NXP LS1028A RDB board Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
74 lines
1.0 KiB
Plaintext
74 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for NXP LS1028A RDB Board.
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*
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* Copyright 2018 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a.dtsi"
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/ {
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model = "LS1028A RDB Board";
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compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
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aliases {
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serial0 = &duart0;
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serial1 = &duart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x1 0x0000000>;
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};
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};
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&i2c0 {
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status = "okay";
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i2c-mux@77 {
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compatible = "nxp,pca9847";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x02>;
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current-monitor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <500>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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};
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};
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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