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When the CONTINUE bit is set, the interrupt status we are polling to identify if a transaction has finished can be sporadic. Even though the transfer has finished, the interrupt status may erroneously indicate that there is still data in the FIFO. This behaviour causes random timeouts in large PIO transfers. Instead of using the CONTINUE bit to control the CS lines, use the SPI core's CS GPIO handling. Also, now that the CONTINUE bit is not being used, we can poll for the ALLDONE interrupt to indicate transfer completion. Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
IMG Synchronous Peripheral Flash Interface (SPFI) controller
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Required properties:
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- compatible: Must be "img,spfi".
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- reg: Must contain the base address and length of the SPFI registers.
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- interrupts: Must contain the SPFI interrupt.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clock/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- spfi: SPI operating clock
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- sys: SPI system interface clock
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- dmas: Must contain an entry for each entry in dma-names.
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See ../dma/dma.txt for details.
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- dma-names: Must include the following entries:
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- rx
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- tx
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- cs-gpios: Must specify the GPIOs used for chipselect lines.
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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Optional properties:
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- img,supports-quad-mode: Should be set if the interface supports quad mode
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SPI transfers.
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Example:
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spi@18100f00 {
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compatible = "img,spfi";
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reg = <0x18100f00 0x100>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&spi_clk>, <&system_clk>;
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clock-names = "spfi", "sys";
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dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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