Christoph Hellwig 9e80635619 riscv: clear the instruction cache and all registers when booting ... When we get booted we want a clear slate without any leaks from previous supervisors or the firmware. Flush the instruction cache and then clear all registers to known good values. This is really important for the upcoming nommu support that runs on M-mode, but can't really harm when running in S-mode either. Vaguely based on the concepts from opensbi. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-17 15:17:39 -08:00
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asm	riscv: clear the instruction cache and all registers when booting	2019-11-17 15:17:39 -08:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00