mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 20:16:54 +07:00
fbd1cec570
Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
145 lines
3.4 KiB
Plaintext
145 lines
3.4 KiB
Plaintext
/*
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* Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
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*/
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/include/ "skeleton_hs_idu.dtsi"
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/ {
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compatible = "snps,arc";
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#address-cells = <2>;
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#size-cells = <2>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
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input_clk: input-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333333>;
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};
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core_clk: core-clk@80 {
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compatible = "snps,axs10x-arc-pll-clock";
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reg = <0x80 0x10>, <0x100 0x10>;
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#clock-cells = <0>;
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clocks = <&input_clk>;
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/*
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* Set initial core pll output frequency to 100MHz.
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* It will be applied at the core pll driver probing
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* on early boot.
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*/
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assigned-clocks = <&core_clk>;
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assigned-clock-rates = <100000000>;
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};
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core_intc: archs-intc@cpu {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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#interrupt-cells = <1>;
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};
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/*
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* this GPIO block ORs all interrupts on CPU card (creg,..)
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* to uplink only 1 IRQ to ARC core intc
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*/
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dw-apb-gpio@0x2000 {
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compatible = "snps,dw-apb-gpio";
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reg = < 0x2000 0x80 >;
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#address-cells = <1>;
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#size-cells = <0>;
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ictl_intc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&idu_intc>;
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interrupts = <1>;
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};
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33333000>;
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interrupt-parent = <&ictl_intc>;
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interrupts = <2 4>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupt-parent = <&core_intc>;
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interrupts = <20>;
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};
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};
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/*
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* This INTC is actually connected to DW APB GPIO
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* which acts as a wire between MB INTC and CPU INTC.
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* GPIO INTC is configured in platform init code
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* and here we mimic direct connection from MB INTC to
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* CPU INTC, thus we set "interrupts = <0 1>" instead of
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* "interrupts = <12>"
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*
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* This intc actually resides on MB, but we move it here to
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* avoid duplicating the MB dtsi file given that IRQ from
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* this intc to cpu intc are different for axs101 and axs103
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*/
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0x0 0xe0012000 0x0 0x200 >;
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interrupt-controller;
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interrupt-parent = <&idu_intc>;
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interrupts = <0>;
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};
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memory {
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device_type = "memory";
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/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
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0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* Move frame buffer out of IOC aperture (0x8z-0xAz).
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*/
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frame_buffer: frame_buffer@be000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xbe000000 0x0 0x2000000>;
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no-map;
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};
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};
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};
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